MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 160

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8
8.1.8.2
This 8-bit read/write register contains the count of external input events at the PAI input, or the
accumulated count. In gated time accumulation mode, PACNT is readable even if PAI is not active.
The counter is not affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading occur during opposite
half cycles.
8.1.8.3
The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF are located within timer
registers TMSK2 and TFLG2.
8.1.8.4
8.1.8.5
PAOVI and PAOVF — Pulse accumulator interrupt enable and overflow flag
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To
clear this status bit, write a one in the corresponding data bit position (bit 5) of the TFLG2 register.
The PAOVI control bit allows the pulse accumulator overflow to be configured for polled or
interrupt-driven operation and does not affect the state of PAOVF. When PAOVI is zero, pulse
accumulator overflow interrupts are inhibited, and the system operates in a polled mode, which
requires that PAOVF be polled by user software to determine when an overflow has occurred.
When the PAOVI control bit is set, a hardware interrupt request is generated each time PAOVF is
set. Before leaving the interrupt service routine, software must clear PAOVF.
MOTOROLA
8-26
Pulse accumulator count (PACNT)
Timer interrupt mask 2 (TMSK2)
Timer interrupt ßag 2 (TFLG2)
PACNT — Pulse accumulator count register
Pulse accumulator status and interrupt bits
TMSK2 — Timer interrupt mask 2 register
TFLG2 — Timer interrupt flag 2 register
Address
Address
Address
$0027
$0024
$0025
(bit 7)
TOF
bit 7
bit 7
bit 7
TOI
TIMING SYSTEM
RTIF PAOVF PAIF
bit 6
bit 6
bit 6
RTII
(6)
PAOVI
bit 5
bit 5
bit 5
(5)
bit 4
bit 4
bit 4
PAII
(4)
bit 3
bit 3
bit 3
(3)
0
0
bit 2
bit 2
bit 2
(2)
0
0
PR1
bit 1
bit 1
bit 1
(1)
0
MC68HC11PH8
(bit 0) undeÞned
bit 0
bit 0
PR0
bit 0
0
0000 0000
0000 0000
on reset
on reset
on reset
State
State
State
TPG