MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 162

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8
8.2.1
Figure 8-5 shows the block diagram of the PWM timer subsystem. Three different clock sources
are selectable and provide inputs to the control registers. Each of the four channels has a counter,
a period register, and a duty register. The waveform output is the result of a match between the
period register (PWPERx) and the value in the counter (PWCNTx). The duty register (PWDTYx)
changes the state of the output during the period to determine the duty cycle.
8.2.2
This register contains bits for selecting the 16-bit PWM options and the prescaler values for the clocks.
8.2.2.1
The PWCLK register contains two control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 3 and 4 are concatenated with the CON34 bit, and
channels 1 and 2 are concatenated with the CON12 bit.
When the 16-bit concatenated mode is selected, the clock source is determined by the low order
channel. Channel 2 is the low order channel when channels 1 and 2 are concatenated. Channel
4 is the low order channel when channels 3 and 4 are concatenated. The pins associated with
channels 1 and 3 can be used for general-purpose I/O when 16-bit PWM mode is selected.
Channel 1 registers are the high order byte of the double-byte channel when channels 1 and 2 are
concatenated. Channel 3 registers are the high order byte of the double-byte channel when
channels 3 and 4 are concatenated. Reads of the high order byte cause the low order byte to be
latched for one cycle to guarantee that double byte reads are accurate. Writes to the low byte of the
counter cause reset of the entire counter. Writes to the upper bytes of the counter have no effect.
CON34 — Concatenate channels 3 and 4
When concatenated, channel 3 is the high-order byte and the channel 4 pin (PH3) is the output.
CON12 — Concatenate channels 1 and 2
When concatenated, channel 1 is the high-order byte and the channel 2 pin (PH1) is the output.
MOTOROLA
8-28
Pulse width clock select (PWCLK)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
PWM timer block diagram
PWCLK — PWM clock prescaler and 16-bit select register
16-bit PWM function
–
–
Channels 3 and 4 are concatenated into one 16-bit PWM channel.
Channels 3 and 4 are separate 8-bit PWMs.
Channels 1 and 2 are concatenated into one 16-bit PWM channel.
Channels 1 and 2 are separate 8-bit PWMs.
Address
$0060 CON34 CON12 PCKA2 PCKA1
bit 7
TIMING SYSTEM
bit 6
bit 5
bit 4
bit 3
0
PCKB3 PCKB2 PCKB1 0000 0000
bit 2
bit 1
MC68HC11PH8
bit 0
on reset
State
TPG