MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 165

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8.2.3
PCLK[4:3] — Pulse width channel 4/3 clock select
PCLK[2:1] — Pulse width channel 2/1 clock select
PPOL[4:1] — Pulse width channel x polarity
Each channel has a polarity bit that allows a cycle to start with either a high or a low level. This is
shown on the block diagram, Figure 8-5, as a selection of either the Q output or the Q output of the
PWM output flip flop. When one of the bits in the PWPOL register is set, the associated PWM channel
output is high at the beginning of the clock cycle, then goes low when the duty count is reached.
8.2.4
Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result
by two. If PWSCAL = $00, clock A is divided by 256, then divided by two to generate clock S.
MC68HC11PH8
Pulse width polarity select (PWPOL)
Pulse width scale (PWSCAL)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
PWPOL — PWM timer polarity & clock source select register
PWSCAL — PWM timer prescaler register
–
–
–
Clock S is source.
Clock B is source.
Clock S is source.
Clock A is source.
PWM channel x output is high at the beginning of the clock cycle and
goes low when duty count is reached.
PWM channel x output is low at the beginning of the clock cycle and
goes high when duty count is reached.
Address
Address
$0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
$0062
(bit 7)
bit 7
bit 7
TIMING SYSTEM
bit 6
bit 6
(6)
bit 5
bit 5
(5)
bit 4
bit 4
(4)
bit 3
bit 3
(3)
bit 2
bit 2
(2)
bit 1
bit 1
(1)
(bit 0) 0000 0000
bit 0
bit 0
MOTOROLA
on reset
on reset
State
State
TPG
8-31
8