MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 167

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8.2.6
Each channel has its own counter which can be read at any time without affecting the count or the
operation of the PWM channel. Writing to a counter causes it to be reset to $00; this is generally
done before the counter is enabled. A counter may also be written to whilst it is enabled; this may
cause a truncated PWM period.
8.2.7
There is one period register for each channel. The value in this register determines the period of
the associated PWM timer channel. PWPERx is connected internally to a buffer which compares
directly with the counter register. The period value in PWPERx is loaded into the buffer when the
counter is cleared by the termination of the previous period or by a write to the counter. This
register can be written at any time, and the written value will take effect from the start of the next
PWM timer cycle. Reads of this register return the most recent value written.
MC68HC11PH8
Pulse width period 1 (PWPER1)
Pulse width period 2 (PWPER2)
Pulse width period 3 (PWPER3)
Pulse width period 4 (PWPER4)
Pulse width count 1 (PWCNT1)
Pulse width count 2 (PWCNT2)
Pulse width count 3 (PWCNT3)
Pulse width count 4 (PWCNT4)
PWCNT1–4 — PWM timer counter registers 1 to 4
PWPER1–4 — PWM timer period registers 1 to 4
Address
Address
$006A
$006B
$0064
$0065
$0066
$0067
$0068
$0069
(bit 7)
(bit 7)
(bit 7)
(bit 7)
(bit 7)
(bit 7)
(bit 7)
(bit 7)
bit 7
bit 7
TIMING SYSTEM
bit 6
bit 6
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
bit 5
bit 5
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
bit 4
bit 4
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
bit 3
bit 3
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
bit 2
bit 2
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
bit 1
bit 1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(bit 0) 0000 0000
(bit 0) 0000 0000
(bit 0) 0000 0000
(bit 0) 0000 0000
(bit 0) 1111 1111
(bit 0) 1111 1111
(bit 0) 1111 1111
(bit 0) 1111 1111
bit 0
bit 0
MOTOROLA
on reset
on reset
State
State
TPG
8-33
8