MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 168

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8
8.2.8
There is one duty register for each channel. The value in this register determines the duty cycle of
the associated PWM timer channel. PWDTYx is compared to the counter contents and if they are
equal, a match occurs and the output goes to the state defined by the associated polarity bit. If the
register is written while the channel is enabled, then the new value is held in a buffer until the counter
rolls over or the channel is disabled. Reads of this register return the most recent value written.
Note:
8.2.9
The following boundary conditions apply to the values stored in the PWDTYx and PWPERx
registers and the PPOLx bits:
•
•
•
•
•
•
MOTOROLA
8-34
Pulse width duty 1 (PWDTY1)
Pulse width duty 2 (PWDTY2)
Pulse width duty 3 (PWDTY3)
Pulse width duty 4 (PWDTY4)
If PWDTYx = $00, PWPERx > $00 and PPOLx = 0 then the output is always high.
If PWDTYx = $00, PWPERx > $00 and PPOLx = 1 then the output is always low.
If PWDTYx
If PWDTYx
If PWPERx = $00 and PPOLx = 0 then the output is always low.
If PWPERx = $00 and PPOLx = 1 then the output is always high.
If PWDTYx PWPERx then there will be no change of state due to the duty cycle value.
In addition, if the duty register is set to $00, then the output will always be in the state
which would normally be result from the duty change of state (see also Section 8.2.9).
PWMx
PWDTY1–4 — PWM timer duty cycle registers 1 to 4
Boundary cases
PWPERx and PPOLx = 0 then the output is always low.
PWPERx and PPOLx = 1 then the output is always high.
Address
$006C
$006D
$006E
$006F
PWDTYx
Figure 8-6 PWM duty cycle
(bit 7)
(bit 7)
(bit 7)
(bit 7)
bit 7
TIMING SYSTEM
bit 6
(6)
(6)
(6)
(6)
PWPERx
bit 5
(5)
(5)
(5)
(5)
bit 4
(4)
(4)
(4)
(4)
bit 3
(3)
(3)
(3)
(3)
bit 2
(2)
(2)
(2)
(2)
bit 1
(1)
(1)
(1)
(1)
MC68HC11PH8
(bit 0) 1111 1111
(bit 0) 1111 1111
(bit 0) 1111 1111
(bit 0) 1111 1111
bit 0
on reset
State
TPG