MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 182

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

9
9.3.2
There are two types of multiple-channel operation. In the first type (SCAN = 0), a selected group
of four channels is converted once only. The first result is stored in A/D result register 1 (ADR1),
and the fourth result is stored in ADR4. After the fourth conversion is complete, all conversion
activity is halted until a new conversion command is written to the ADCTL register. In the second
type of multiple-channel operation (SCAN = 1), conversions continue to be performed on the
selected group of channels with the fifth conversion being stored in register ADR1 (replacing the
earlier conversion result for the first channel in the group), the sixth conversion overwriting ADR2,
and so on.
9.4
9.4.1
All bits in this register can be read or written, except bit 7, which is a read-only status indicator,
and bit 6, which always reads as zero. Write to ADCTL to initiate a conversion. To quit a conversion
in progress, write to this register and a new conversion sequence begins immediately.
CCF — Conversions complete flag
A read-only status indicator, this bit is set when all four A/D result registers contain valid
conversion results. Each time the ADCTL register is overwritten, this bit is automatically cleared
to zero and a conversion sequence is started. In the continuous mode, CCF is set at the end of
the first conversion sequence.
Bit 6 — Not implemented; always reads zero.
SCAN — Continuous scan control
When this control bit is clear, the four requested conversions are performed once to fill the four
result registers. When this control bit is set, the four conversions are repeated continuously with
the result registers updated as data becomes available.
MOTOROLA
9-8
A/D control & status (ADCTL)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Multiple-channel operation
Control, status and results registers
ADCTL — A/D control and status register
–
–
All four A/D result registers contain valid conversion data.
At least one of the A/D result registers contains invalid data.
A/D conversions take place continuously.
Each of the four conversions is performed only once.
Address
ANALOG-TO-DIGITAL CONVERTER
$0030
CCF
bit 7
bit 6
0
SCAN MULT
bit 5
bit 4
bit 3
CD
bit 2
CC
bit 1
CB
MC68HC11PH8
bit 0
CA
u0uu uuuu
on reset
State
TPG