MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 186

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

10
10.1.2
The CPU distinguishes between internal and external reset conditions by sensing whether the
reset pin rises to a logic one in less than four E clock cycles after an internal device releases reset.
When a reset condition is sensed, the RESET pin is driven low by an internal device for eight E
clock cycles, then released. Four E clock cycles later it is sampled. If the pin is still held low, the
CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor. It is not advisable to connect an
external resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices
because the circuit charge time constant can cause the device to misinterpret the type of reset
that occurred. To guarantee recognition of an external reset, the RESET pin should be held low
for at least 16 clock cycles.
10.1.3
The MCU includes a COP system to help protect against software failures. When the COP is
enabled, the software is responsible for keeping a free-running watchdog timer from timing out.
When the software is no longer being executed in the intended sequence, a system reset is
initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP system is
enabled or disabled. To change the enable status of the COP system, change the contents of the
CONFIG register and then perform a system reset. In the special test and bootstrap operating
modes, the COP system is initially inhibited by the disable resets (DISR) control bit in the TEST1
register. The DISR bit can subsequently be written to zero to enable COP resets.
The COP function has two possible clock sources. When PLL clock generation is not used
(VDDSYN = 0), the clocking chain for the COP function is tapped off from the main timer divider
chain (E/2
function can be clocked by the underflow of the 8-bit modulus timer A (CLK64/4); see Figure 8-2.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP timeout
period. The COP clock source frequency is scaled by the factor shown in Table 10-1 or Table 10-2.
After reset, bits CR[1:0] are zero, which selects the shortest timeout period. In normal operating
modes, these bits can only be written once, within 64 bus cycles after reset.
MOTOROLA
10-2
15
); refer to Figure 8-1. When the PLL clock generation is used (VDDSYN = 1), the COP
External reset (RESET)
COP reset
RESETS AND INTERRUPTS
MC68HC11PH8
TPG