MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 187

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MC68HC711PH8

Manufacturer Part Number
MC68HC711PH8
Description
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
Manufacturer
Motorola
Datasheet
10.1.3.1
Complete the following reset sequence to service the COP timer. Write $55 to COPRST to arm
the COP timer clearing mechanism. Then write $AA to COPRST to clear the COP timer. Executing
instructions between these two steps is possible as long as both steps are completed in the
correct sequence before the timer times out.
MC68HC11PH8
COP timer arm/reset (COPRST)
COPRST — Arm/reset COP timer circuitry register
(1) The timeout period has a tolerance of Ð0/+one cycle of the CLK64/4 clock due to
CR[1:0]
(1) The timeout period has a tolerance of Ð0/+one cycle of the E/2
CR[1:0]
0 0
0 1
1 0
1 1
the asynchronous implementation of the COP circuitry. For example, with
CLK64 = 64 Hz, the uncertainty is Ð0/+62.5ms. See also the M68HC11
Reference Manual, (M68HC11RM/AD).
0 0
0 1
1 0
1 1
the asynchronous implementation of the COP circuitry. For example, with
EXTALi = 8MHz, the uncertainty is Ð0/+16.384ms. See also the M68HC11
Reference Manual, (M68HC11RM/AD).
Table 10-1 COP timer rate select (PLL disabled)
Table 10-2 COP timer rate select (PLL enabled)
CLK64 by
E/2
Divide
Divide
256
16
64
E =
4
16
64
Address
15
1
4
$003A
by
RESETS AND INTERRUPTS
EXTALi = 8MHz:
CLK64 = 4.096 kHz:
16.384 ms
65.536 ms
262.14 ms
(bit 7)
timeout
1.049 sec
bit 7
2.0 MHz
timeout
62.5 sec
15.6 ms
3.9 ms
1 ms
(1)
bit 6
(1)
(6)
EXTALi = 12MHz:
bit 5
(5)
10.923 ms
43.691 ms
174.76 ms
699.05 ms
timeout
3.0 MHz
CLK64 =64 Hz:
timeout
62.5 ms
250 ms
bit 4
1 s
4 s
(4)
(1)
(1)
bit 3
EXTALi = 16MHz:
(3)
32.768 ms
131.07 ms
524.29 ms
timeout
15
8.192 ms
CLK64 = 4 Hz:
4.0 MHz
clock due to
timeout
bit 2
(2)
16 s
64 s
1 s
4 s
(1)
(1)
bit 1
(1)
(bit 0) not affected
bit 0
MOTOROLA
on reset
State
TPG
10-3
10

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