MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 189

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

IRQE — Configure IRQ for falling edge sensitive operation (Refer to Section 3)
DLY — Enable oscillator start-up delay
Note:
A mask option on the MC68HC11PH8 allows the selection of either a short or long delay time for
power-on reset and exit from STOP mode; either 128 or 4064 bus cycles. This option is not
available on the MC68HC711PH8 where the delay time is 4064 bus cycles.
CME — Clock monitor enable
This control bit can be read or written at any time and controls whether or not the internal clock
monitor circuit triggers a reset sequence when the system clock is slow or absent. When it is clear,
the clock monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled. Reset
clears the CME bit.
In order to use both STOP and clock monitor, the CME bit should be cleared before executing
STOP, then set again after recovering from STOP.
FCME — Force clock monitor enable
When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
STOP mode, FCME should always be cleared.
CR[1:0] — COP timer rate select bits
The COP function can be clocked either by the internal E clock divided by 2
the 8-bit modulus timer A, CLK64/4. These control bits determine a scaling factor for the watchdog
timer period. See Table 10-1 and Table 10-2.
MC68HC11PH8
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Because DLY is set on reset, a delay is always imposed as the MCU is started up from
power-on reset.
–
–
–
–
Falling edge sensitive operation.
Low level sensitive operation.
A stabilization delay is imposed as the MCU is started up from STOP
mode (or from power-on reset).
The oscillator start-up delay is bypassed and the MCU resumes
processing within about four bus cycles. A stable external oscillator
is required if this option is selected.
Clock monitor enabled.
Clock monitor disabled.
Clock monitor enabled; cannot be disabled until next reset.
Clock monitor follows the state of the CME bit.
RESETS AND INTERRUPTS
15
, or by the output of
MOTOROLA
TPG
10-5
10