MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 215

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

11.1.6.1
The C-bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic
operation. The C-bit also acts as an error flag for multiply and divide operations. Shift and rotate
instructions operate with and through the carry bit to facilitate multiple-word shift operations.
11.1.6.2
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V-bit is cleared.
11.1.6.3
The Z-bit is set if the result of an arithmetic, logic, or data manipulation operation is zero.
Otherwise, the Z-bit is cleared. Compare instructions do an internal implied subtraction and the
condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX,
INY, and DEY) affect the Z-bit and no other condition flags. For these operations, only = and
conditions can be determined.
11.1.6.4
The N-bit is set if the result of an arithmetic, logic, or data manipulation operation is negative;
otherwise, the N-bit is cleared. A result is said to be negative if its most significant bit (MSB) is set
(MSB = 1). A quick way to test whether the contents of a memory location has the MSB set is to
load it into an accumulator and then check the status of the N-bit.
11.1.6.5
The interrupt request (IRQ) mask (I-bit) is a global mask that disables all maskable interrupt
sources. While the I-bit is set, interrupts can become pending, but the operation of the CPU
continues uninterrupted until the I-bit is cleared. After any reset, the I-bit is set by default and can
only be cleared by a software instruction. When an interrupt is recognized, the I-bit is set after the
registers are stacked, but before the interrupt vector is fetched. After the interrupt has been
serviced, a return from interrupt instruction is normally executed, restoring the registers to the
values that were present before the interrupt occurred. Normally, the I-bit is zero after a return from
interrupt is executed. Although the I-bit can be cleared within an interrupt service routine, ‘nesting’
interrupts in this way should only be done when there is a clear understanding of latency and of
the arbitration mechanism. Refer to Section 10.
MC68HC11PH8
Carry/borrow (C)
Overflow (V)
Zero (Z)
Negative (N)
Interrupt mask (I)
CPU CORE AND INSTRUCTION SET
MOTOROLA
TPG
11-5
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