MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 216

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

11
11.1.6.6
The H-bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an
ADD, ABA, or ADC instruction. Otherwise, the H-bit is cleared. Half carry is used during BCD
operations.
11.1.6.7
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set by default
and must be cleared by a software instruction. When an XIRQ interrupt is recognized, the X- and
I-bits are set after the registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed, causing the registers to be
restored to the values that were present before the interrupt occurred. The X interrupt mask bit is
set only by hardware RESET or XIRQ acknowledge). X is cleared only by program instruction
(TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value loaded into the CCR from
the stack has been cleared). There is no hardware action for clearing X.
11.1.6.8
Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 into a
low-power stop condition. If the STOP instruction is encountered by the CPU while the S-bit is set,
it is treated as a no-operation (NOP) instruction, and processing continues to the next instruction.
S is set by reset — STOP disabled by default.
11.2
The M68HC11 CPU supports the following data types:
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•
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A byte is eight bits wide and can be accessed at any byte location. A word is composed of two
consecutive bytes with the most significant byte at the lower value address. Because the
M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or
operands.
MOTOROLA
11-6
Bit data
8-bit and 16-bit signed and unsigned integers
16-bit unsigned fractions
16-bit addresses
Half carry (H)
X interrupt mask (X)
Stop disable (S)
Data types
CPU CORE AND INSTRUCTION SET
MC68HC11PH8
TPG