MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 224

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

11
MOTOROLA
11-14
Operators
Cycles
SUBA (opr)
SUBB (opr)
SUBD (opr)
Mnemonic
TST (opr)
XGDX
TEST
TSTB
XGDY
TSTA
TBA
TSX
TSY
TXS
TYS
SWI
TAB
TAP
TPA
WAI
+
Ð
à
*
¥
:
Is transferred to
Boolean AND
Arithmetic addition, except where used as an
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction, or negation symbol
InÞnite, or until reset occurs
12 cycles are used, beginning with the opcode
inclusive-OR symbol in Boolean formulae
(Twos complement)
fetch. A wait state is entered, which remains
in effect for an integer number of MPU E clock
cycles (n) until an interrupt is recognised.
Finally, two additional cycles are used to fetch
the appropriate interrupt vector. (14 + n, total).
Transfer stack pointer to X
Transfer stack pointer to Y
Transfer X to stack pointer
Transfer Y to stack pointer
Subtract memory from A
Subtract memory from B
Subtract memory from D
Transfer A to CC register
Test (only in test modes)
Transfer CC register to A
Test A for zero or minus
Test B for zero or minus
Test for zero or minus
Exchange D with X
Exchange D with Y
Software interrupt
Wait for interrupt
Transfer A to B
Transfer B to A
Operation
Table 11-2 Instruction set (Sheet 6 of 6)
CPU CORE AND INSTRUCTION SET
address bus increments
stack registers & WAIT
D Ð M:M+1
IX
IY
see Figure 11-2
SP + 1
SP + 1
IX Ð 1
IY Ð 1
Description
A Ð M
B Ð M
A
CCR
A
B
M Ð 0
A Ð 0
B Ð 0
D; D
D; D
CCR
B
A
SP
SP
A
A
B
IX
IY
IX
IY
D
Operands
Condition Codes
mm
A
A
A
A
A
B
B
B
B
B
A
B
dd
hh
kk
Ñ
rr
ff
0
1
?
Addressing
ii
jj
ll
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
INH
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
INH
INH
INH
INH
mode
8-bit direct address ($0000Ð$00FF); the high byte is assumed
8-bit positive offset ($00 to $FF (0 to 256)) is added to the
High order byte of 16-bit extended address
One byte of immediate data
High order byte of 16-bit immediate data
Low order byte of 16-bit immediate data
Low order byte of 16-bit extended address
8-bit mask (set bits to be affected)
Signed relative offset ($80 to $7F (Ð128 to +127));
Bit not changed
Bit always cleared
Bit always set
Bit set or cleared, depending on the operation
Bit can be cleared, but cannot become set
Not deÞned
to be zero
contents of the index register
offset is relative to the address following the offset byte
Opcode
18 A0
18 E0
18 A3
18 6D
18 30
18 35
18 8F
80
90
B0
A0
C0
D0
F0
E0
83
93
B3
A3
3F
16
06
17
00
07
7D
6D
4D
5D
30
35
3E
8F
Instruction
Operand
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj
dd
hh ll
ff
ff
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
hh ll
ff
ff
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
kk
Cycles
14
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
2
2
2
6
6
7
2
2
3
4
3
4
à
3
4
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ 1 Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
S X H I N Z V C
MC68HC11PH8
Condition codes
0 Ñ
0 Ñ
0 0
0 0
0 0
TPG