MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 33

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

2.5.1
The voltage controlled oscillator (VCO) generates the PLL output frequency VCOOUT. This signal
is fed back through a frequency divider, which divides the signal frequency by a factor determined
by the contents of the SYNR register, to produce the feedback signal f
phase detector along with the reference signal, f
signal (PCOMP) which is a function of the phase difference between f
integrated, and the resultant dc voltage (visible on XFC) is applied to the VCO, modifying the
output signal VCOOUT to lock it in phase with f
Note:
The state of two bits in the PLLCR register, MCS and BCS, determine whether VCOOUT or
EXTALi is used for the system clocks.
A mask option on the MC68HC11PH8 allows the PLL circuit to be optimized for operation in either
of two frequency ranges, as shown in Table 2-1 (this option is not available on the
MC68HC711PH8; on this device the PLL is optimized for operation at 32kHz) . Input frequencies
other than those included in Table 2-1 can be used, but, for operation above the maximum
frequency specified, VDDSYN should be grounded to disable the PLL and enable the high
frequency oscillator circuit; in this state the oscillator is designed for 16MHz operation and XFC
may be left unconnected. Refer also to Figure 2-5.
VDDSYN is the power supply pin for the PLL and should be suitably bypassed. Connecting it high
enables the internal low frequency oscillator circuitry designed for the PLL. The external capacitor
on XFC (C
a larger capacitor will improve the PLL’s frequency stability, at the expense of increasing the time
required for it to settle (t
adequate for either 32kHz or 614kHz applications. Refer to Section A.5.2 for PLL control timing
information.
The PLL filter has two bandwidths that can be manually selected under control of the BWC bit in
PLLCR. Whenever the PLL is first enabled, the wide bandwidth mode should be used, to enable
the PLL frequency to ramp up quickly. After a time t
the narrow bandwidth mode, to make the final frequency more stable.
Warning: Bit 5 of the PLLCR (AUTO) must be cleared before an attempt is made to use BWC;
MC68HC11PH8
Because the operation of the PLL depends on repeated adjustments to the voltage
input to the VCO, a time t
manual bandwidth control should always be used.
XFC
PLL operation
) should be located as close to the chip as possible to minimize noise. In general,
Typical input frequency
Maximum input frequency
PLLS
) at the desired frequency. A capacitor value of 47nF is usually
Characteristic
Table 2-1 PLL mask options
PLLS
PIN DESCRIPTIONS
is required for the stabilization of the output frequency.
REF
Mask option 1 Mask option 2
.
REF
PLLS
32 kHz
50 kHz
. The phase detector generates a control
has elapsed, the filter can be switched to
614 kHz
2 MHz
FB
FB
. This signal is input to the
and f
REF
. PCOMP is then
MOTOROLA
TPG
2-7
2