MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 36

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

2
BWC — Bandwidth control
Bandwidth selection can only be controlled by BWC when AUTO is cleared. After the PLL is first
enabled, or after a change in frequency, a delay of t
bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on
or off. Reset clears this bit.
VCOT — VCO test (Test mode only)
This bit is used to isolate the loop filter from the VCO for testing purposes. VCOT is always set in
user modes. This bit is writable only in bootstrap and test modes. Reset sets this bit.
MCS — Module clock select
Reset clears this bit.
T16EN — 16-bit timer clock enable (refer to Section 8)
WEN — WAIT enable
This bit determines whether the 4XCLK is disconnected from VCOOUT during WAIT and
connected to EXTALi. Reset clears this bit.
When WEN is set, the CPU will respond to a WAIT instruction by first stacking the relevant
registers, then by clearing BCS and setting the PLL to ‘idle’, with modulus = 1. BWC is set so that
the wide bandwidth control is selected.
Any interrupt, any reset, or the assertion of RAF (receiver active flag) in either of the SCIs will allow
the PLL to resume operating at the frequency specified in the SYNR. The user must set BCS after
the PLL has had time to adjust (t
then RAF cannot become set, hence the PLL will not resume normal operation. For a description
of RAF and RE, see Section 5.
MOTOROLA
2-10
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
–
–
–
–
–
Wide (high and low) bandwidth control selected.
Narrow (low) bandwidth control selected.
Loop filter operates as specified by AUTO and BWC.
Low bandwidth mode of the PLL filter is disabled.
4XCLK is the source for the SCI and timer divider chain.
EXTALi is the source for the SCI and timer divider chain.
16-bit timer clock enabled.
16-bit timer clock disabled.
Low-power WAIT mode selected (PLL set to ‘idle’ in WAIT mode).
Do not alter the 4XCLK during WAIT mode.
PLLS
). If, for a specific SCI, the RE bit (receiver enable bit) is clear,
PIN DESCRIPTIONS
PLLS
is required before clearing BWC. The low
MC68HC11PH8
TPG