MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 42

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

2
2.11.3
Port C is an 8-bit general purpose I/O port with a data register (PORTC) and a data direction
register (DDRC). In single chip mode, port C pins are general purpose I/O pins (PC[7:0]). In the
expanded mode, port C pins are configured as data bus pins (D[7:0]).
PORTC can be read at any time and always returns the pin level. If PORTC is written, the data is
stored in internal latches. The pins are driven only if they are configured as outputs in single chip
or bootstrap mode. Port C pins are general purpose inputs out of reset in single chip and bootstrap
modes. In expanded and test modes, these pins are data bus lines out of reset.
The CWOM control bit in the OPT2 register disables port C’s p-channel output drivers. Because
the n-channel driver is not affected by CWOM, setting CWOM causes port C to become an
open-drain-type output port suitable for wired-OR operation. In wired-OR mode (PORTC bits at
logic level zero), the pins are actively driven low by the n-channel driver. When a port C bit is at
logic level one, the associated pin is in a high impedance state as neither the n-channel nor the
p-channel devices are active. It is customary to have an external pull-up resistor on lines that are
driven by open-drain devices. Port C can only be configured for wired-OR operation when the
MCU is in single chip mode. For further information, refer to Section 4.
2.11.4
Port D, a 6-bit general purpose I/O port, has a data register (PORTD) and a data direction register
(DDRD). The six port D lines (D[5:0]) can be used for general purpose I/O, for one of the serial
communications interfaces (SCI1, pins [1,0]) and for one of the serial peripheral interfaces (SPI1,
pins [5:2]).
PORTD can be read at any time; inputs return the pin level and outputs return the pin driver input
level. If PORTD is written, the data is stored in internal latches. The pins are driven only if port D
is configured for general purpose output.
The DWOM bit in SPCR disables the p-channel output drivers of pins D[5:2], and the WOMS bit
in SCCR1 disables those of pins D[1,0]. Because the n-channel driver is not affected by DWOM
or WOMS, setting either bit causes the corresponding port D pins to become open-drain-type
outputs suitable for wired-OR operation. In wired-OR mode (PORTD bits at logic level zero), the
pins are actively driven low by the n-channel driver. When a port D bit is at logic level one, the
associated pin is in a high impedance state as neither the n-channel nor the p-channel devices
are active. It is customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation when the MCU is in single chip mode
or expanded mode.
For further information, refer to Section 4, Section 5 (SCI) and Section 7 (SPI).
MOTOROLA
2-16
Port C
Port D
PIN DESCRIPTIONS
MC68HC11PH8
TPG