MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 62

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

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08/Apr/97@13:55 [DS97 v 4.1]
3.3.2.3
This register determines the location of EEPROM in the memory map and controls stretching of
external accesses. INIT2 may be read at any time but bits 7–4 may be written only once after reset
in normal modes (bits 3, 1 and 0 may be written at any time).
EE[3:0] — EEPROM map position
EEPROM is located at $xD00–$xFFF, where x is the hexadecimal digit represented by EE[3:0].
Refer to Table 3-6.
STRX — Stretch extended
This bit only has meaning in expanded mode, and only if the STRCH bit in OPT2 is set (see
Section 3.3.2.5).
Bit 2 — Not implemented; always reads zero.
M2DL1, M2DL0 — MI BUS delay select (refer to Section 6)
MOTOROLA
3-16
†
EEPROM mapping (INIT2)
1 (set)
0 (clear) –
This bit is not present on early versions of the MC68HC711PH8. On those devices, bit 3 is not
implemented and always reads zero, and the stretch function is controlled solely by the
STRCH bit in OPT2 (see Section 3.3.2.5). Contact your local Motorola Sales Representative
for further information.
INIT2 — EEPROM mapping and MI BUS delay register
–
All external accesses are extended by one E clock cycle.
Only external access from $0000 to $1FFF (ROMAD set) or from
$C000 to $DFFF (ROMAD clear) are extended by one E clock cycle.
OPERATING MODES AND ON-CHIP MEMORY
†
EE[3:0]
Address
—this line does not form part of the document—
$0037
0000
0001
0010
0011
0100
0101
0110
0111
Table 3-6 EEPROM remapping
$0D00Ð$0FFF
$1D00Ð$1FFF
$2D00Ð$2FFF
$3D00Ð$3FFF
$4D00Ð$4FFF
$5D00Ð$5FFF
$6D00Ð$6FFF
$7D00Ð$7FFF
bit 7
EE3
Location
bit 6
EE2
EE[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
bit 5
EE1
$CD00Ð$CFFF
$DD00Ð$DFFF
$AD00Ð$AFFF
$BD00Ð$BFFF
$ED00Ð$EFFF
bit 4
EE0
$8D00Ð$8FFF
$9D00Ð$9FFF
$FD00Ð$FFFF
Location
STRX
bit 3
bit 2
0
M2DL1 M2DL0 0000 0000
bit 1
PH8.DS03/Modes+mem
MC68HC11PH8
bit 0
on reset
State
TPG