MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 66

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

10
12
13
14
15
11
1
2
3
4
5
6
7
8
9
08/Apr/97@13:55 [DS97 v 4.1]
LSBF — LSB-first enable (refer to Section 7)
SPR2 — SPI clock rate select (refer to Section 7)
This bit adds a divide-by-four to the SPI clock chain.
EXT4X — 4XLCK or EXTAL clock output select
This bit can be written once and can be read at any time.
This bit selects which clock is to be output on the 4XOUT pin, when enabled by the CLK4X bit in
CONFIG (see Section 3.3.2.1). On reset, or when BCS = 0, 4XCLK (the PLL output) is the same
as EXTALi. Refer to Section 2-6. There is a phase delay between EXTALi and 4XOUT.
Note:
DISE — E clock output disable
This bit can be written once and can be read at any time.
IRVNE allows E clock to be turned off in single chip modes. DISE has been added for expanded
modes, but can be used in every mode. Writing a zero to this bit prevents accidental E clock
turn-off in systems requiring this signal.
MOTOROLA
3-20
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
The 4XOUT pin is not available on 84-pin packaged devices.
–
–
–
Single chip
Expanded
Boot
Special test
Mode
Data is transferred LSB first.
Data is transferred MSB first.
EXTALi clock output on the 4XOUT pin.
4XCLK clock output on the 4XOUT pin.
No E clock output.
E clock is output normally.
OPERATING MODES AND ON-CHIP MEMORY
after reset
—this line does not form part of the document—
IRVNE
0
0
0
1
after reset
E clock
On
On
On
On
after reset
IRV
Off
Off
Off
On
affects only
IRVNE
IRV
IRV
E
E
can be written
Unlimited
Unlimited
IRVNE
Once
Once
PH8.DS03/Modes+mem
MC68HC11PH8
TPG