MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 112
MC68HC711xxxx
Manufacturer Part Number
MC68HC711xxxx
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC711XXXX.pdf
(268 pages)
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Parallel Input/Output (I/O) Ports
6.5 Port D
Data Sheet
112
Alternate Function:
PORTCL is used in the handshake clearing mechanism. When an active edge
occurs on the STRA pin, port C data is latched into the PORTCL register. Reads
of this register return the last value latched into PORTCL and clear STAF flag
(following a read of PIOC with STAF set).
DDRC[7:0] — Port C Data Direction Bits
In all modes, port D bits [5:0] can be used either for general-purpose I/O or with the
serial communications interface (SCI) and serial peripheral interface (SPI)
subsystems. During reset, port D pins PD[5:0] are configured as high-impedance
inputs (DDRD bits cleared).
Address:
Address:
In the 3-state variation of output handshake mode, clear the corresponding
DDRC bits. Refer to
Timing Diagram (STRA Enables Output
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Reset:
Read:
Write:
0 = Input
1 = Output
I = Indeterminate after reset
DDRC7
$1005
$1007
PCL7
Bit 7
Bit 7
$1008
Bit 7
0
—
—
Figure 6-6. Port C Data Direction Register (DDRC)
0
Figure 6-5. Port C Latched Register (PORTCL)
Figure 6-7. Port D Data Register (PORTD)
Parallel Input/Output (I/O) Ports
DDRC6
PCL6
6
6
0
—
—
6
0
Figure 10-13. 3-State Variation of Output Handshake
DDRC5
PCL5
PD5
PD5
5
5
0
SS
5
I
Indeterminate after reset
DDRC4
PCL4
SCK
PD4
PD4
4
4
0
4
I
Buffer).
DDRC3
PCL3
MOSI
PD3
PD3
3
3
0
3
I
DDRC2
PCL2
MISO
M68HC11E Family — Rev. 5
PD2
PD2
2
2
0
2
I
DDRC1
PCL1
PD1
PD1
1
1
0
Tx
1
I
MOTOROLA
DDRC0
PCL0
Bit 0
Bit 0
Bit 0
PD0
PD0
RxD
0
I
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