MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 138

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

Serial Peripheral Interface (SPI)
8.7 SPI Registers
8.7.1 Serial Peripheral Control Register
Data Sheet
138
The three SPI registers are:
These registers provide control, status, and data storage functions.
SPIE — Serial Peripheral Interrupt Enable Bit
SPE — Serial Peripheral System Enable Bit
DWOM — Port D Wired-OR Mode Bit
MSTR — Master Mode Select Bit
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•
•
Set the SPE bit to 1 to request a hardware interrupt sequence each time the
SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or
if the I bit in the condition code register is 1.
When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the
SPI function. If the SPI is in the master mode and DDRD bit 5 is set, then the
port D bit 5 pin becomes a general-purpose output instead of the SS input.
DWOM affects all port D pins.
It is customary to have an external pullup resistor on lines that are driven by
open-drain devices.
Address:
Reset:
Read:
Write:
0 = SPI system interrupts disabled
1 = SPI system interrupts enabled
0 = SPI system disabled
1 = SPI system enabled
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data register (SPDR)
U = Unaffected
$1028
SPIE
Figure 8-3. Serial Peripheral Control Register (SPCR)
Bit 7
0
Serial Peripheral Interface (SPI)
SPE
6
0
DWOM
5
0
MSTR
4
0
CPOL
3
0
CPHA
M68HC11E Family — Rev. 5
2
1
SPR1
U
1
MOTOROLA
SPR0
Bit 0
U