MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 152

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

Timing System
9.4.3 Output Compare Mask Register
9.4.4 Output Compare Data Register
9.4.5 Timer Counter Register
Data Sheet
152
Use OC1M with OC1 to specify the bits of port A that are affected by a successful
OC1 compare. The bits of the OC1M register correspond to PA[7:3].
OC1M[7:3] — Output Compare Masks
Bits [2:0] — Unimplemented
Use this register with OC1 to specify the data that is to be stored on the affected
pin of port A after a successful OC1 compare. When a successful OC1 compare
occurs, a data bit in OC1D is stored in the corresponding bit of port A for each bit
that is set in OC1M.
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1
compares.
Bits [2:0] — Unimplemented
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer.
A full counter read addresses the most significant byte (MSB) first. A read of this
address causes the least significant byte (LSB) to be latched into a buffer for the
Always read 0
Always read 0
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
0 = OC1 disabled
1 = OC1 enabled to control the corresponding pin of port A
OC1M7
OC1D7
$100C
$100D
Figure 9-13. Output Compare 1 Mask Register (OC1M)
Figure 9-14. Output Compare 1 Data Register (OC1D)
Bit 7
Bit 7
0
0
= Unimplemented
= Unimplemented
OC1M6
OC1D6
6
0
6
0
Timing System
OC1M5
OC1D5
5
0
5
0
OC1M4
OC1D4
4
0
4
0
OC1M3
OC1D3
3
0
3
0
M68HC11E Family — Rev. 5
2
0
2
0
1
0
1
0
MOTOROLA
Bit 0
Bit 0
0
0