MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 156
MC68HC711xxxx
Manufacturer Part Number
MC68HC711xxxx
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC711XXXX.pdf
(268 pages)
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Timing System
9.4.10 Timer Interrupt Flag Register 2
9.5 Real-Time Interrupt (RTI)
Data Sheet
156
Bits in this register indicate when certain timer system events have occurred.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer
subsystem to operate in either a polled or interrupt driven system. Each bit of
TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Unimplemented
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a
fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the
pulse accumulator control (PACTL) register. The RTII bit in the TMSK2 register
enables the interrupt capability. The four different rates available are a product of
the MCU oscillator frequency and the value of bits RTR[1:0]. Refer to
which shows the periodic real-time interrupt rates.
Set when TCNT changes from $FFFF to $0000
Refer to
Refer to
Refer to
Always read 0
Address:
Reset:
RTR[1:0]
Read:
Write:
0 0
0 1
1 0
1 1
9.5 Real-Time Interrupt
9.7 Pulse
9.7 Pulse
$1025
Bit 7
TOF
Figure 9-20. Timer Interrupt Flag 2 Register (TFLG2)
0
E = 3 MHz
10.923 ms
21.845 ms
= Unimplemented
2.731 ms
5.461 ms
RTIF
Accumulator.
Accumulator.
6
0
Timing System
PAOVF
Table 9-5. RTI Rates
5
0
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
(RTI).
PAIF
4
0
3
0
E = 1 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
M68HC11E Family — Rev. 5
2
0
1
0
E = X MHz
(E/2
(E/2
(E/2
(E/2
Table
MOTOROLA
13
14
15
16
)
)
)
)
Bit 0
0
9-5,
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