MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 50

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

Operating Modes and On-Chip Memory
2.3.3.2 RAM and I/O Mapping Register
Data Sheet
50
NOSEC — Security Disable Bit
NOCOP — COP System Disable Bit
ROMON — ROM/EPROM/OTPROM Enable Bit
EEON — EEPROM Enable Bit
The internal registers used to control the operation of the MCU can be relocated
on 4-Kbyte boundaries within the memory space with the use of the RAM and I/O
mapping register (INIT). This 8-bit special-purpose register can change the default
locations of the RAM and control registers within the MCU memory map. It can be
written only once within the first 64 E-clock cycles after a reset in normal modes,
and then it becomes a read-only register.
RAM[3:0] — RAM Map Position Bits
NOSEC is invalid unless the security mask option is specified before the MCU
is manufactured. If the security mask option is omitted NOSEC always reads 1.
The enhanced security feature is available in the MC68S711E9 MCU. The
enhancement to the standard security feature protects the EPROM as well as
RAM and EEPROM.
Refer to
When this bit is 0, the ROM or EPROM is disabled and that memory space
becomes externally addressed. In single-chip mode, ROMON is forced to 1 to
enable ROM/EPROM regardless of the state of the ROMON bit.
When this bit is 0, the EEPROM is disabled and that memory space becomes
externally addressed.
These four bits, which specify the upper hexadecimal digit of the RAM address,
control position of RAM in the memory map. RAM can be positioned at the
beginning of any 4-Kbyte page in the memory map. It is initialized to address
$0000 out of reset. Refer to
Address: $103D
Reset:
Read:
Write:
0 = Security enabled
1 = Security disabled
1 = COP disabled
0 = COP enabled
0 = ROM disabled from the memory map
1 = ROM present in the memory map
0 = EEPROM removed from the memory map
1 = EEPROM present in the memory map
Section 5. Resets and
RAM3
Bit 7
Operating Modes and On-Chip Memory
0
Figure 2-12. RAM and I/O Mapping Register (INIT)
RAM2
6
0
RAM1
Table
5
0
Interrupts.
2-4.
RAM0
4
0
REG3
3
0
REG2
M68HC11E Family — Rev. 5
2
0
REG1
1
0
MOTOROLA
REG0
Bit 0
1