MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 66

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

Analog-to-Digital (A/D) Converter
3.2.6 Conversion Sequence
3.3 A/D Converter Power-Up and Clock Select
Data Sheet
66
E CLOCK
0
CHANNEL, UPDATE
CONVERT FIRST
SAMPLE ANALOG INPUT
ADR1
A/D converter operations are performed in sequences of four conversions each. A
conversion sequence can repeat continuously or stop after one iteration. The
conversion complete flag (CCF) is set after the fourth conversion in a sequence to
show the availability of data in the result registers.
a typical sequence. Synchronization is referenced to the system E clock.
12 E CYCLES
Bit 7 of the OPTION register controls A/D converter power-up. Clearing ADPU
removes power from and disables the A/D converter system. Setting ADPU
enables the A/D converter system. Stabilization of the analog bias voltages
requires a delay of as much as 100 µs after turning on the A/D converter. When the
A/D converter system is operating with the MCU E clock, all switching and
comparator operations are inherently synchronized to the main MCU clocks. This
allows the comparator output to be sampled at relatively quiet times during MCU
clock cycles. Since the internal RC oscillator is asynchronous to the MCU clock,
there is more error attributable to internal system clock noise. A/D converter
accuracy is reduced slightly while the internal RC oscillator is being used
(CSEL = 1).
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes
Address: $1039
Reset:
Read:
Write:
Figure 3-4. System Configuration Options Register (OPTION)
32
Figure 3-3. A/D Conversion Sequence
ADPU
CONVERT SECOND
CHANNEL, UPDATE
Bit 7
0
Analog-to-Digital (A/D) Converter
ADR2
CYCLES
= Unimplemented
MSB
CSEL
4
6
0
SUCCESSIVE APPROXIMATION SEQUENCE
BIT 6
CYC
64
2
IRQE
BIT 5
CYC
CHANNEL, UPDATE
5
0
CONVERT THIRD
2
(1)
BIT 4
CYC
ADR3
2
DLY
BIT 3
CYC
4
1
2
(1)
BIT 2
CYC
2
96
CME
BIT 1
CYC
3
0
CHANNEL, UPDATE
CONVERT FOURTH
Figure 3-3
2
CYC
LSB
ADR4
2
M68HC11E Family — Rev. 5
CYC
END
2
0
2
shows the timing of
128 — E CYCLES
CR1
1
0
(1)
MOTOROLA
CR0
Bit 0
0
(1)