MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 67

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MC68HC711xxxx

Manufacturer Part Number
MC68HC711xxxx
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
3.4 Conversion Process
3.5 Channel Assignments
M68HC11E Family — Rev. 5
MOTOROLA
ADPU — A/D Power-Up Bit
CSEL — Clock Select Bit
IRQE — Configure IRQ for Edge-Sensitive Only Operation
DLY — Enable Oscillator Startup Delay Bit
CME — Clock Monitor Enable Bit
Bit 2 — Not implemented
CR[1:0] — COP Timer Rate Select Bits
The A/D conversion sequence begins one E-clock cycle after a write to the A/D
control/status register, ADCTL. The bits in ADCTL select the channel and the mode
of conversion.
An input voltage equal to V
converts to $FF (full scale), with no overflow indication. For ratiometric conversions
of this type, the source of each analog input should use V
and be referenced to V
The multiplexer allows the A/D converter to select one of 16 analog signals. Eight
of these channels correspond to port E input lines to the MCU, four of the channels
are internal reference points or test functions, and four channels are reserved.
Refer to
Refer to
Refer to
Always reads 0
Refer to
0 = A/D powered down
1 = A/D powered up
0 = A/D and EEPROM use system E clock.
1 = A/D and EEPROM use internal RC clock.
0 = The oscillator startup delay coming out of stop is bypassed and the MCU
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is
Table
resumes processing within about four bus cycles.
started up from the stop power-saving mode. This delay allows the
crystal oscillator to stabilize.
Section 5. Resets and
Section 5. Resets and
Section 5. Resets and Interrupts
3-1.
Analog-to-Digital (A/D) Converter
RL
.
RL
converts to $00 and an input voltage equal to V
Interrupts.
Interrupts.
and
Section 9. Timing
Analog-to-Digital (A/D) Converter
RH
as the supply voltage
Conversion Process
System.
Data Sheet
RH
67

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