MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 79

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

4.4 Opcodes and Operands
4.5 Addressing Modes
4.5.1 Immediate
M68HC11E Family — Rev. 5
MOTOROLA
A byte is eight bits wide and can be accessed at any byte location. A word is
composed of two consecutive bytes with the most significant byte at the lower
value address. Because the M68HC11 is an 8-bit CPU, there are no special
requirements for alignment of instructions or operands.
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode
identifies a particular instruction and associated addressing mode to the CPU.
Several opcodes are required to provide each instruction with a range of
addressing capabilities. Only 256 opcodes would be available if the range of values
were restricted to the number able to be expressed in 8-bit binary numbers.
A 4-page opcode map has been implemented to expand the number of
instructions. An additional byte, called a prebyte, directs the processor from page
0 of the opcode map to one of the other three pages. As its name implies, the
additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two,
or three operands. The operands contain information the CPU needs for executing
the instruction. Complete instructions can be from one to five bytes long.
Six addressing modes can be used to access memory:
These modes are detailed in the following paragraphs. All modes except inherent
mode use an effective address. The effective address is the memory address from
which the argument is fetched or stored or the address from which execution is to
proceed. The effective address can be specified within an instruction, or it can be
calculated.
In the immediate addressing mode, an argument is contained in the byte(s)
immediately following the opcode. The number of bytes following the opcode
matches the size of the register or memory location being operated on. There are
2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective
address is the address of the byte following the instruction.
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Immediate
Direct
Extended
Indexed
Inherent
Relative
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcodes and Operands
Data Sheet
79