MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 96

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

Resets and Interrupts
5.4 Reset and Interrupt Priority
Data Sheet
96
Resets and interrupts have a hardware priority that determines which reset or
interrupt is serviced first when simultaneous requests occur. Any maskable
interrupt can be given priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is:
The maskable interrupt sources have this priority arrangement:
Any one of these interrupts can be assigned the highest maskable interrupt priority
by writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise,
the priority arrangement remains the same. An interrupt that is assigned highest
priority is still subject to global masking by the I bit in the CCR, or by any associated
local bits. Interrupt vectors are not affected by priority assignment. To avoid race
conditions, HPRIO can be written only while I-bit interrupts are inhibited.
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system (refer to
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
Resets and Interrupts
Figure
5-7)
M68HC11E Family — Rev. 5
MOTOROLA