XC73144-10 Xilinx, XC73144-10 Datasheet

XC73144-10

Manufacturer Part Number

XC73144-10

Description

144-Macrocell CMOS EPLD

Manufacturer

Xilinx

Datasheet

1.XC73144-10.pdf (11 pages)

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• High-Performance EPLD

• Advanced Dual-Block architecture

• 100% interconnect matrix

• High-Speed arithmetic carry network

• 144 Macrocells with programmable I/O architecture

• Up to 132 inputs programmable as direct, latched, or

• All outputs with 24 mA drive

• 3.3 V or 5 V I/O operation

• Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V

• Power management options

• Multiple security bits for design protection

• 160-pin plastic quad flat pack and 225-pin ball-grid-

• 100% PCI compliant

• Programmable slew rate

• Programmable ground control

General Description

The XC73144 is a member of the Xilinx Dual-Block EPLD

family. It consists of four Fast Function Blocks and twelve

High-Density Function Blocks interconnected by a central

Universal Interconnect Matrix (UIM).

The sixteen Function Blocks in the XC73144 are PAL-like

structures, complete with programmable product term

arrays and programmable multilevel Macrocells. Each

Function Block receives 24 inputs, contains nine Macro-

cells conﬁgurable for registered or combinatorial logic and

produces nine outputs which feedback to the UIM and

output pins.

Features

– 7.5 ns pin-to-pin speed on all fast inputs

– 100 MHz maximum clock frequency

– Four Fast Function Blocks

– Twelve High-Density Function Blocks

– 1 ns ripple-carry delay per bit

– 43 MHz 16-bit accumulators

registered

array packages

This document was created with FrameMaker 4 0 2

2-65

Product Speciﬁcations

XC73144

144-Macrocell CMOS EPLD

The Universal Interconnect Matrix connects the Function

Blocks to each other and to all input pins, providing 100%

connectivity between the Function Blocks. This allows

logic functions to be mapped into the Function Blocks and

interconnected without routing restrictions.

The XC73144 is designed in a 0.8

nology.

In addition, the XC73144 includes a programmable power

management feature to specify high-performance or low-

power operation on an individual Macrocell-by-Macrocell

basis. Unused Macrocells are automatically turned off to

minimize power dissipation. Designers can operate

speed-critical paths at maximum performance, while non-

critical paths dissipate less power.

Xilinx development software (XEPLD) supports all mem-

bers of XC7300 family. The designer can create, imple-

ment, and verify digital logic circuits for EPLD devices

using the Xilinx XEPLD Development System. Designs

can be represented as schematics consisting of XEPLD

library components, as behavioral descriptions, or as a

mixture of both. The XEPLD translator automatically per-

forms logic optimization, collapsing, mapping and routing

without user intervention. After compiling the design,

XEPLD translator produces documentation for design

analysis and creates a programming ﬁle to conﬁgure the

device.

The following lists some of the XEPLD Development Sys-

tem features.

• Familiar design approach similar to TTL and PLD

• Converts netlist to fuse map in minutes using a 386/

• Interfaces to standard third-party CAE schematics,

• Timing simulation using Viewsim, OrCAD VST, Mentor,

techniques

486 PC or workstation platform

simulation tools, and behavioral languages

LMC and other tools compatible with the Xilinx Netlist

Format (XNF)

CMOS EPROM tech-

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