XC7336-10 Xilinx, XC7336-10 Datasheet
XC7336-10
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XC7336-10 Summary of contents
Page 1
... The XC7336 is designed in 0.8 ogy, in speed grades ranging from 5 to15 ns. The XC7336Q is also available now, providing lower power consumption in -10, -12 and -15 ns speed grades. Device logic is automatically configured to the user’s speci- fi ...
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... The Macrocell output can also be routed back as an input to the Fast Function Block, and the UIM. Power-On Characteristics/Master Reset The XC7336 device undergoes a short internal initializa- tion sequence upon device powerup. During this time (t ), the outputs remain 3-stated while the device is SET confi ...
Page 3
... I/O can also safely interface to a mixed 3.3 V and 5 V bus simultaneously. Low Power (Q) Devices The XC7336-10, -12 and -15 are available in a low power variant, designated the XC7336Q. Timing parameters for the XC7336 and the XC7336Q devices are identical. However, the XC7336Q features much lower power consumption ...
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... Macrocells in high-performance mode Macrocells in low-power mode Total number of Macrocells used f = Clock frequency (MHz) Figure 4 shows a typical power calculation for the XC7336 device, programmed as two 16-bit counters and operating at the indicated clock frequency. 200 150 100 Clock Frequency (MHz) Figure 4 ...
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... Macrocell requirements and increase speed. Notice: The information contained in this data sheet pertains to products in the initial production phases of development. These specifications are subject to change without notice. Verify with your local Xilinx sales office that you have the latest data sheet before finalizing a design. ...
Page 6
... XC7336 CMOS EPLD DC Characteristics Over Recommended Operating Conditions Symbol Parameter 5 V TTL High-level output voltage V OH 3.3 V High-level output voltage 5 V TTL Low-level output voltage V OL 3.3 V Low-level output voltage I Input leakage current IL I Output high-Z leakage current OZ C Input capacitance for Input and I/O pins ...
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... Output FCLK TEST R 1 Device Output Device Input Rise and Fall Times < 3ns V Level CCIO TEST 5.0 V 160 120 3.3 V 3.3 V 260 360 2-29 XC7336-10 XC7336-12 XC7336-15 Min Max Min Max Min 10.0 12.0 15.0 19.0 5.0 6.0 7.0 10.0 13.0 15 8.0 9.0 10.0 12.0 10.0 12.0 100.0 80.0 66.7 5.0 5.5 6 FOD FOE ...
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... Max 1.0 1.5 5 2.0 3.5 2.5 1.5 1.0 2.5 1.0 1.0 0.5 0.5 2.0 2.0 0.6 0.8 0.5 4.0 XC7336-5 XC7336-7 Min Max Min Max 1.5 2.5 2.0 3.0 3.5 4.5 1.5 1.5 2-30 t FSUI t FOUT t FCOI t FPDI t FHI t FAOI XC7336-10 XC7336-12 XC7336-15 Min Max Min Max Min Max 1.5 2.0 2.0 5.5 7.0 8.0 2.5 3.0 4.0 2.5 3.0 3.0 1.0 1.0 1.0 0.5 1.0 1.0 2.5 3.0 4.0 1.0 1.2 1.5 5.0 6.5 8.0 XC7336-10 XC7336-12 XC7336-15 Min Max Min Max Min Max 3.5 4.0 5.0 4.5 5.0 7.0 5.0 7.0 8.0 2.5 3.0 4.0 Pin X5221 Units Units ...
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Combinatorial Switching Characteristics Input, I/O Pin UIM Delay Logic Delay P-Term Assignment Delay Transparent Register Delay Output Buffer Output Pin Asynchronous Clock Switching Characteristics Input, I/O Pin t IN Input, I/O Delay UIM Delay Clock at Register Data from Logic ...
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... XC7336 CMOS EPLD Synchronous Clock Switching Characteristics F Pin CLK Data/CE at Input I/O Register Input, I/O Register to UIM Fast Clock Input Delay Data at Input I/O Pin Data at Input Register Register to Output Pin PQ44 PC44 Input 39 1 I/FO/ I/FO/ I/FO/ I/FO/ FO/FCLK0 44 6 FO/FCLK1 1 7 I/FO/ I/FO 3 ...
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... Commercial = 0° to +70° Industrial = -40° to 85°C The Programmable Logic Company SM XC7336 - Temperature Range Speed Number of Pins Package Type Low Power -10, -12, -15 speeds 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay 7 ...
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... XC7336 CMOS EPLD 2-34 ...