PALCE16V8H-10JC Advanced Micro Devices, PALCE16V8H-10JC Datasheet

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PALCE16V8H-10JC

Manufacturer Part Number
PALCE16V8H-10JC
Description
EE CMOS 20-Pin Universal Programmable Array Logic
Manufacturer
Advanced Micro Devices
Datasheet

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PALCE16V8 Family
EE CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. The PALCE16V8 will directly replace the
PAL16R8 and PAL10H8 series devices, with the excep-
tion of the PAL16C1.
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
2-36
Pin and function compatible with all 20-pin
GAL devices
Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for the PAL16R8
series and most of the PAL10H8 series
Outputs programmable as registered or
combinatorial in any combination
Peripheral Component Interconnect (PCI)
compliant
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/25, Q-20/25
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial with an active-
high or active-low output. The output configuration is
determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
AMD’s FusionPLD program allows PALCE16V8 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and
SOIC packages
Extensive third-party software and programmer
support through FusionPLD partners
Fully tested for 100% programming and
functional yields and high reliability
5 ns version utilizes a split leadframe for
improved performance
Publication# 16493
Issue Date: February 1996
Rev. D
Amendment /0

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PALCE16V8H-10JC Summary of contents

Page 1

FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS Pin and function compatible with all 20-pin GAL devices Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology ...

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BLOCK DIAGRAM MACRO MACRO OE/I I/O I CONNECTION DIAGRAMS Top View DIP/SOIC CLK I I ...

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... PC, JC, SC, PI, JI PALCE16V8Q-15 PC, JC PALCE16V8Q-20 PI, JI PALCE16V8H-25 PC, JC, SC, PI, JI PALCE16V8Q-25 PC, JC, PI, JI 2-38 PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com’l) PAL Valid Combinations lists configurations planned / supported in volume for this device. Consult the local AMD sales office to confirm availability of /4 specific valid combinations and to check on newly /5 released combinations ...

Page 4

FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device. It has eight independently configurable macrocells (MC Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated in- put. The programming matrix implements a program- mable AND ...

Page 5

AMD Configuration Options Each macrocell can be configured as one of the follow- ing: registered output, combinatorial output, combinato- rial I/O, or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the ...

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CLK Registered Active Low Combinatorial I/O Active Low V CC Combinatorial Output Active Low Notes: 1. Feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. This configuration is not available ...

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AMD Power-Up Reset All flip-flops power logic LOW for predictable sys- tem initialization. Outputs of the PALCE16V8 will de- pend on whether they are selected as registered or combinatorial. If registered is selected, the output will be ...

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LOGIC DIAGRAM CLK ...

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AMD LOGIC DIAGRAM (continued ...

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... (Note 0 Max (Note 3) OUT CC Outputs Open ( mA), V OUT V = Max CC and I (or I and OZL IH OZH PALCE16V8H-5 (Com’l) AMD ) Operating + with +4. +5.25 V Min Max 2.0 0.8 10 –100 10 –100 –30 – ...

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... Test Conditions MHz OUT LOW HIGH External Feedback 1/( Internal Feedback (f ), 1/(t +t CNT Feedback 1/( PALCE16V8H-5 (Com’l) Typ Unit = Min (Note 5) Max Unit 142 ...

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... (Note 0 Max (Note 3) OUT CC Outputs Open mA), OUT V = Max MHz CC and I (or I and OZL IH OZH PALCE16V8H-7 (Com’l) AMD ) + +4. +5.25 V Min Max 2.0 0.8 10 –100 10 –100 –30 –150 ...

Page 13

... Test Conditions MHz OUT 8 Outputs Switching 1 Output Switching 1/( 1/( (Note 6) CNT S CF 1/( PALCE16V8H-7 (Com’l) Typ Unit = Min (Note 5) Max Unit 3 7 ...

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... 0 Max (Note 3) OUT CC Outputs Open ( mA) OUT V = Max MHz CC and I (or I and OZL IH OZH PALCE16V8H-10 (Com’l, Ind) AMD ) Operating + with +4. +5. Operating A – + with +4 +5.5 V Min Max ...

Page 15

... MHz OUT LOW HIGH External Feedback 1/( Internal Feedback (f ) 1/( (Note 5) CNT Feedback 1/( PALCE16V8H-10 (Com’l, Ind) Typ Unit = Min (Note 4) Max Unit 66.7 MHz 71.4 MHz ) 83.3 MHz ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to Ground ...

Page 17

AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Descriptions C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance ...

Page 18

... Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second 0.5 V has been chosen to avoid test problems caused by tester ground degradation. OUT PALCE16V8H-15/25, Q-15/25 (Com’l, Ind), Q-20 (Ind) OPERATING RANGES – +150 C Commercial (C) Devices Temperature (T – ...

Page 19

... These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected calculated value and is not guaranteed can be found using the following equation 1/f MAX (internal feedback) – 2-54 PALCE16V8H-15/25, Q-15/25 (Com’l, Ind), Q-20 (Ind) Test Conditions ...

Page 20

SWITCHING WAVEFORMS Input Feedback Combinatorial Output Combinatorial Output t WH Clock Clock Width Output Notes 1 Input pulse amplitude 3 Input rise and fall times 2 ...

Page 21

AMD KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT Specification Closed Open Closed Open Closed 2-56 WAVEFORM INPUTS Must be Steady May ...

Page 22

TYPICAL I CHARACTERISTICS 150 125 100 I (mA The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were ...

Page 23

AMD ENDURANCE CHARACTERISTICS The PALCE16V8 is manufactured using AMD’s ad- vanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Symbol Parameter t Min Pattern Data Retention Time DR N Min Reprogramming ...

Page 24

... Protection and Clamping * Rev Letter Device Filter Only PALCE16V8H- PALCE16V8H- PALCE16V8Q- PALCE16V8H- PALCE16V8Q- clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insen- sitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 versions ...

Page 25

AMD POWER-UP RESET The PALCE16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature pro- vides ...

Page 26

... Symbol Parameter Description Thermal Impedance, Junction to Case jc Thermal Impedance, Junction to Ambient ja Thermal Impedance, Junction to Ambient with Air Flow jma /5 Devices (PALCE16V8H-7/5) Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal Impedance, Junction to Case jc Thermal Impedance, Junction to Ambient ...

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