LTC4266 LINER [Linear Technology], LTC4266 Datasheet - Page 25

• Manufacturer Part Number: LTC4266
• Description: Quad IEEE 802.3at Power over Ethernet Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Four commonly available 1Ω resistors (0402 or larger
package size) can be used in parallel in place of a single
0.25Ω resistor. In order to meet the I
required by the IEEE specification, the sense resistors
should have ±1% tolerance or better, and no more than
±200ppm/°C temperature coefficient.
Output Cap
Each port requires a 0.22μF cap across its outputs to keep
the LTC4266 stable while in current limit during startup
or overload. Common ceramic capacitors often have sig-
nificant voltage coefficients; this means the capacitance
is reduced as the applied voltage increases. To minimize
this problem, X7R ceramic capacitors rated for at least
100V are recommended.
ESD/Cable Discharge Protection
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thou-
sands of volts, are plugged into the low impedance of the
RJ45 jack. To protect against damage, each port requires a
pair of clamp diodes; one to AGND and one to V
10). An additional surge suppressor is required for each
LTC4266 chip from V
steer harmful surges into the supply rails, where they are
absorbed by the surge suppressor and the V
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4266 from transients on the
V
EE
supply.
EE
I
CROSSTALK ERROR
1
+ I
to AGND. The diodes at the ports
2
SCALE ERROR
+ I
I
EE
EE
LTC4266
SIGNAL
SENSE
V
GATE
EE
–
V
R
+
V
Figure 19. Layout Affects Current Readback Accuracy
CUT
S
S
M
= I
1
R
and I
S1
MUTUAL RESISTANCE
+ I
R
I
1
1
S1
R
LIM
M
I
2
+ I
EE
EE
accuracy
2
R
R
S2
(Figure
bypass
M
S1B diodes work well as port clamp diodes, and an
SMAJ58A or equivalent is recommended for the V
suppressor.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4266:
place the decoupling caps for the V
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
The main layout challenge involves the arrangement of
the current sense resistors, and their connections to
the LTC4266. Because the sense resistor values are very
low, layout parasitics can cause significant errors. Care is
required to achieve specified accuracy, particularly with
disconnect currents.
Figure 19 illustrates the problem. In the example on the
left, two ports have load currents I
the V
R
planes, and vias in the PCB that I
return to the V
age difference between its SENSE and V
the voltage drop across R
R
The example on the right shows how errors can be
minimized with a good layout. The circuit is rearranged
so that R
to the LTC4266 is used as a Kelvin sense trace. V
M
M
I
SMALL OFFSET ERROR
EE
introduces errors.
represents the combined resistances of any traces,
LTC4266
EE
SENSE
V
GATE
EE
–
power supply through a mutual resistance R
KELVIN SENSE LINE
M
+
V
R
no longer affects V
S
K
SIGNAL
EE
supply. The LTC4266 measures the volt-
V
R
I
S
1
S1
= I
I
2
1
R
S1
R
I
1
– I
S2
S1
+ I
EE
R
, but as the example shows,
2
M
R
+ I
K
4266 F19
S
EE
, and the V
1
1
and I
DD
and I
LTC4266
and V
EE
2
2
EE
share as they
that return to
pins to sense
EE
connection
supplies
EE
EE
25
surge
is not
4266fb
M
.