ICS83056AI01 ICST [Integrated Circuit Systems], ICS83056AI01 Datasheet

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ICS83056AI01

Manufacturer Part Number
ICS83056AI01
Description
6-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
G
The output has a V
1.8V, making the device ideal for use in voltage translation ap-
plications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug. Possible applications include systems with up to 6 trans-
ceivers which need to be independently set for different rates.
For example, a board may have six transceivers, each of which
need to be independently configured for 1 Gigabit Ethernet or
1 Gigabit Fibre Channel rates. Another possible application may
require the ports to be independently set for FEC (Forward Er-
ror Correction) or non-FEC rates. The device operates up to
250MHz and is packaged in a 20 TSSOP.
B
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83056AGI-01
HiPerClockS™
ICS
LOCK
ENERAL
CLK0
CLK1
SEL0
SEL5
OE
D
clock inputs and six single-ended clock outputs.
The ICS83056I-01 is a 6-bit, 2:1, Single-ended Mul-
tiplexer and a member of the HiPerClockS™ fam-
ily of High Performance Clock Solutions from ICS.
The ICS83056I-01 has two selectable single-ended
Pulldown
Pulldown
Pullup
Integrated
Circuit
Systems, Inc.
IAGRAM
D
Pulldown
Pulldown
ESCRIPTION
DDO
pin which may be set at 3.3V, 2.5V, or
0
1
0
1
PRELIMINARY
www.icst.com/products/hiperclocks.html
Q0
Q5
1
F
• 6-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15 (V
• Maximum output frequency: 250MHz
• Propagation delay: 2.5ns (typical)
• Input skew: 45ps (typical)
• Part-to-part skew: TBD
• Operating supply modes:
• -40°C to 85°C ambient operating temperature
P
Additive phase jitter, RMS (12KHz - 20MHz):
0.07ps (typical)
V
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
EATURES
IN
DD
/V
A
6.5mm x 4.4mm x 0.92mm package body
DDO
SSIGNMENT
CLK1
SEL5
SEL4
SEL3
GND
V
ICS83056I-01
V
20-Lead TSSOP
DDO
Q5
Q4
Q3
S
DD
G Package
INGLE
Top View
1
2
3
4
5
6
7
8
9
10
ICS83056I-01
-E
20
19
18
17
16
15
14
13
12
11
NDED
DDO
SEL0
Q0
V
GND
Q1
SEL1
CLK0
OE
Q2
SEL2
DDO
=3 .3V)
REV. A FEBRUARY 7, 2005
M
6-B
ULTIPLEXER
IT
, 2:1,

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ICS83056AI01 Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS83056I- 6-bit, 2:1, Single-ended Mul- ICS tiplexer and a member of the HiPerClockS™ fam- ily of High Performance Clock Solutions from ICS. HiPerClockS™ The ICS83056I-01 has two selectable single-ended ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A. P ...

Page 4

Integrated Circuit Systems, Inc. T 4C. LVCMOS/LVTTL DC C ABLE HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc 3.3V ± 5%, V ABLE HARACTERISTICS ...

Page 6

Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...

Page 7

Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...

Page 8

Integrated Circuit Systems, Inc. P ARAMETER 1.65V± DDO LVCMOS GND -1.65V±5% 3.3V C /3. ORE UTPUT OAD 2.05V±5% 1.25V± DDO LVCMOS GND -1.25V±5% 3.3V C /2. ...

Page 9

Integrated Circuit Systems, Inc CLK0, CLK1 2 V DDO Q0: ROPAGATION ELAY CLKx Q0:Q5 t PD1 CLKy Q0:Q5 t PD2 I S NPUT KEW 83056AGI-01 PRELIMINARY 20% Clock Outputs UTPUT ...

Page 10

Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in ...

Page 11

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE S Y Reference Document: JEDEC Publication 95, MO-153 83056AGI-01 PRELIMINARY TSSOP EAD ACKAGE IMENSIONS ...

Page 12

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

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