M29DW128F60NF1 STMICROELECTRONICS [STMicroelectronics], M29DW128F60NF1 Datasheet - Page 35

• Manufacturer Part Number: M29DW128F60NF1
• Description: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29DW128F
6.2.7
6.2.8
6.2.9
Three bus write cycles are necessary to issue the command:
1.
2.
3.
Quadruple Byte Program command
This is used to write four adjacent Bytes in x8 mode, simultaneously. The addresses of the four
Bytes must differ only in A0, DQ15A-1.
Five bus write cycles are necessary to issue the command.
1.
2.
3.
4.
5.
Octuple Byte Program command
This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the
eight Bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When the
cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode.
When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The Unlock Bypass Program command can then be issued to program
addresses within the bank, or the Unlock Bypass Reset command can be issued to return the
bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Byte to be written.
The third bus cycle latches the Address and the Data of the second Byte to be written and
starts the Program/Erase Controller.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Byte to be written.
The third bus cycle latches the Address and the Data of the second Byte to be written.
The fourth bus cycle latches the Address and the Data of the third Byte to be written.
The fifth bus cycle latches the Address and the Data of the fourth Byte to be written and
starts the Program/Erase Controller.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Byte to be written.
The third bus cycle latches the Address and the Data of the second Byte to be written.
The fourth bus cycle latches the Address and the Data of the third Byte to be written.
The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.
The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.
The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.
The eighth bus cycle latches the Address and the Data of the seventh Byte to be written.
The ninth bus cycle latches the Address and the Data of the eighth Byte to be written and
starts the Program/Erase Controller.
6 Command Interface
35/93