M29DW128F60NF1 STMICROELECTRONICS [STMicroelectronics], M29DW128F60NF1 Datasheet - Page 43

• Manufacturer Part Number: M29DW128F60NF1
• Description: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29DW128F
1. Grey cells represent Read cycles. The other cells are Write cycles.
2. SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection Mode Lock bit
3. Addresses are described in
4. During Unlock and Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11
5. A Reset Command must be issued to return to the Read mode.
6. The 4
7. Data is latched on the rising edge of W.
8. The entire command sequence must be entered for each portion of the password.
9. The command sequence returns FFh if the Password Protection Mode locking bit is set.
10. The password is written over four consecutive cycles, at addresses [0-3]
11. A 2µs timeout is required between any two portions of the password.
12. A 10ms delay is required between the 4th and the 5th cycle.
13. A 12ms timeout is required between cycles 4 and 5.
Set Non-
Volatile Modify
Protection Bit
(6)
Verify Non-
Volatile Modify
Protection Bit
Clear Non-
Volatile Modify
Protection
Bits
Set Lock-Down
bit
Verify Lock-
Down bit
Set Lock Bit
Clear Lock
Bit
Verify Lock Bit
Set Standard
Protection
Mode
Verify Standard
Protection
Mode
Command
(7)
Address, PL Password Protection Mode Lock Bit Address, PW Password Data, PWA Password Address, RPW Password
Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address, X Don’t
Care. All values in the table are in hexadecimal.
(except where BA is required) and data bits higher than DQ7 are Don't Care.
Standard Protection Mode Lock bit, and a block NVMP bit). The 5
programmed when DQ0=1. If DQ0=0 in the 6
100µs delay is required between the 4th and the 5th cycle.
(12)(13)(14)
(5)(6)
(5)
(15)
th
Bus Write cycle programs a protection bit (Extended Block Protection bit, Password Protection Mode Lock bit,
(7)
(5)
6
4
6
3
4
4
4
4
6
4
Add Data Add
555
555
555
555
555
555
555
555
555
555
1st
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Table 17: Protection Command
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2nd
Data
55
55
55
55
55
55
55
55
55
55
th
Add Data
555
555
555
555
555
555
555
555
555
555
cycle, the program command must be issued again and verified again. A
3rd
60
60
60
78
58
48
48
58
60
60
Bus Operations
Addresses.
NVMP
NVMP
NVMP
(BA)/
(BA)
Add
BA
BA
BA
BA
SL
SL
/
th
4th
and 6
Data
DQ1
DQ0
DQ0
X1h
X0h
68
48
60
68
th
cycles verify that the bit has been successively
(1)(2)(3)(4)
NVMP
NVMP
NVMP
(BA)/
(BA)/
(BA)/
Add
SL
5th
Data
DQ0
48
40
48
NVMP
NVMP
(BA)/
(BA)/
Add
SL
6 Command Interface
6th
Data
DQ0
DQ0
DQ0
Add
7th
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Data