MC14093BDTR2G

Manufacturer Part NumberMC14093BDTR2G
DescriptionIC SCHMITT TRG QUAD 2INP 14TSSOP
ManufacturerON Semiconductor
Series4000B
MC14093BDTR2G datasheet
 

Specifications of MC14093BDTR2G

Logic TypeNAND Gate - Schmitt TriggerNumber Of Inputs2
Number Of Circuits4Current - Output High, Low3.4mA, 3.4mA
Voltage - Supply3 V ~ 18 VOperating Temperature-55°C ~ 125°C
Mounting TypeSurface MountPackage / Case14-TSSOP
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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MC14093B
Quad 2−Input NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin−for−Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt−Trigger at each Input
Pb−Free Packages are Available
MAXIMUM RATINGS
(Voltages Referenced to V
Symbol
Parameter
V
DC Supply Voltage Range
DD
V
, V
Input or Output Voltage Range
in
out
(DC or Transient)
I
, I
Input or Output Current
in
out
(DC or Transient) per Pin
P
Power Dissipation,
D
per Package (Note 1)
T
Ambient Temperature Range
A
T
Storage Temperature Range
stg
T
Lead Temperature
L
(8−Second Soldering)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
v (V
or V
) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
or V
). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
)
SS
Value
Unit
−0.5 to +18.0
V
−0.5 to V
+ 0.5
V
DD
± 10
mA
500
mW
−55 to +125
°C
−65 to +150
°C
260
°C
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
and V
should be constrained
in
out
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
MC14093BCP
P SUFFIX
AWLYYWWG
CASE 646
1
14
SOIC−14
14093BG
D SUFFIX
AWLYWW
CASE 751A
1
14
14
TSSOP−14
093B
DT SUFFIX
ALYW G
CASE 948G
G
1
14
SOEIAJ−14
MC14093B
F SUFFIX
ALYWG
CASE 965
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Publication Order Number:
MC14093B/D

MC14093BDTR2G Summary of contents

  • Page 1

    MC14093B Quad 2−Input NAND" Schmitt Trigger The MC14093B Schmitt trigger is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. ...

  • Page 2

    ... ORDERING INFORMATION Device MC14093BCP MC14093BCPG MC14093BD MC14093BDG MC14093BDR2 MC14093BDR2G MC14093BDTR2 MC14093BDTR2G MC14093BFEL MC14093BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free OUT D 10 ...

  • Page 3

    ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

  • Page 4

    SWITCHING CHARACTERISTICS Î Î Î Î Î ...

  • Page 5

    All unused inputs connected to ground −5.0 Vdc −2 −55° +25°C A −4 +125° −6.0 −10 Vdc ...

  • Page 6

    −T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

  • Page 7

    ... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

  • Page 8

    ... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...

  • Page 9

    ... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...