MPC9351D

Manufacturer Part NumberMPC9351D
DescriptionLow Voltage PLL Clock Driver
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MPC9351D datasheet
 
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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC9351 is a 2.5V and 3.3V compatible, PLL based clock
generator targeted for high performance clock distribution systems. With
output frequencies of up to 200 MHz and a maximum output skew of 150
ps the MPC9351 is an ideal solution for the most demanding clock tree
designs. The device offers 9 low skew clock outputs, each is configurable
to support the clocking needs of the various high-performance
microprocessors including the PowerQuicc II integrated communication
microprocessor. The extended temperature range of the MPC9351
supports telecommunication and networking requirements.The devices
employs a fully differential PLL design to minimize cycle-to-cycle and
long-term jitter.
Features
9 outputs LVCMOS PLL clock generator
25 - 200 MHz output frequency range
Fully integrated PLL
2.5V and 3.3V compatible
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
32 lead LQFP package
Ambient Temperature Range –40 C to +85 C
Functional Description
The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation
of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The
reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8 the internal VCO of the
MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is
either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and
1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK).
The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the
selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system
diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply.
The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose
lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also
enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5V and 3.3V compatible and requires no external loop
filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50
MPC9351 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm 2
32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC9351 allows the low skew outputs to lock onto a clock input and distribute it with essentially
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
06/01
For More Information On This Product,
Motorola, Inc. 2001
W
transmission lines. For series terminated transmission lines, each of the
1
REV 1
Go to: www.freescale.com
Order this document
by MPC9351/D
MPC9351
LOW VOLTAGE
2.5V AND 3.3V PLL
CLOCK GENERATOR
FA SUFFIX
LQFP PACKAGE
CASE 873A–02

MPC9351D Summary of contents

  • Page 1

    MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC9351 is a 2.5V and 3.3V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies 200 MHz and ...

  • Page 2

    Freescale Semiconductor, Inc. MPC9351 (pullup) PCLK 0 PCLK Ref (pulldown) TCLK 1 (pulldown) REF_SEL (pulldown) EXT_FB FB (pullup) PLL_EN (pulldown) FSELA (pulldown) FSELB (pulldown) FSELC (pulldown) FSELD (pulldown) OE The MPC9351 requires an external RC filter for the analog power ...

  • Page 3

    Freescale Semiconductor, Inc. PIN CONFIGURATION Pin I/O PCLK, PCLK Input LVPECL TCLK Input LVCMOS EXT_FB Input LVCMOS REF_SEL Input LVCMOS FSELA Input LVCMOS FSELB Input LVCMOS FSELC Input LVCMOS FSELD Input LVCMOS OE Input LVCMOS QA Output LVCMOS QB Output ...

  • Page 4

    Freescale Semiconductor, Inc. MPC9351 DC CHARACTERISTICS ( 3.3V Symbol Characteristics V IH Input High Voltage V IL Input Low Voltage V PP Peak-to-Peak Input Voltage PCLK, PCLK V CMR a Common Mode Range PCLK, PCLK V OH Output ...

  • Page 5

    Freescale Semiconductor, Inc. DC CHARACTERISTICS ( 2.5V Symbol Characteristics V IH Input High Voltage V IL Input Low Voltage V PP Peak-to-Peak Input Voltage PCLK, PCLK V CMR a Common Mode Range PCLK, PCLK V OH Output High ...

  • Page 6

    Freescale Semiconductor, Inc. MPC9351 Programming the MPC9351 The MPC9351 clock driver outputs can be configured into several divider modes, in addition the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The output ...

  • Page 7

    Freescale Semiconductor, Inc. Calculation of part-to-part skew The MPC9351 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC9351 are connected ...

  • Page 8

    Freescale Semiconductor, Inc. MPC9351 target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor From the data sheet the I CCA ...

  • Page 9

    Freescale Semiconductor, Inc. 3.0 OutA 3.8956 OutB 2 3.9386 2.0 In 1.5 1.0 0 TIME (nS) Figure 8. Single versus Dual Waveforms Since this step is well above the ...

  • Page 10

    Freescale Semiconductor, Inc. MPC9351 PCLK V CMR PCLK Ext_FB Figure 12. Propagation delay ( static phase offset) test reference 100% The time from the ...

  • Page 11

    Freescale Semiconductor, Inc –T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD For More Information On ...

  • Page 12

    Freescale Semiconductor, Inc. MPC9351 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...