MPC9351D FREESCALE [Freescale Semiconductor, Inc], MPC9351D Datasheet - Page 10

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MPC9351D

Manufacturer Part Number
MPC9351D
Description
Low Voltage PLL Clock Driver
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
MPC9351
MOTOROLA
The deviation in t 0 for a controlled edge with respect to a t 0 mean in a
random sample of cycles
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
TCLK
(PCLK)
Ext_FB
Figure 12. Propagation delay (t PD , static phase
PCLK
PCLK
Ext_FB
Figure 14. Output Duty Cycle (DC)
T N
Figure 16. Cycle–to–cycle Jitter
t P
offset) test reference
T N+1
Figure 18. I/O Jitter
t ( )
T 0
DC = t P /T 0 x 100%
T JIT(CC) = |T N –T N+1 |
Freescale Semiconductor, Inc.
T JIT( ) = |T 0 –T 1 mean|
For More Information On This Product,
V CMR
V CC
V CC
GND
Go to: www.freescale.com
B
2
V CMR
V CC
V CC
GND
B
10
2
TCLK
Ext_FB
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 13. Propagation delay (t PD ) test reference
Figure 15. Output–to–output Skew t SK(O)
t F
Figure 19. Transition Time Test Reference
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
T 0
t ( )
Figure 17. Period Jitter
t SK(O)
t R
T JIT(P) = |T N –1/f 0 |
V CC =3.3V
TIMING SOLUTIONS
0.55
2.4
V CC =2.5V
V CC
V CC
GND
V CC
V CC
GND
V CC
V CC
GND
V CC
V CC
GND
1.8V
0.6V
B
B
B
B
2
2
2
2

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