MPC9351D FREESCALE [Freescale Semiconductor, Inc], MPC9351D Datasheet - Page 4

• Manufacturer Part Number: MPC9351D
• Description: Low Voltage PLL Clock Driver
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MPC9351
a.
b.
a.
b.
DC CHARACTERISTICS (V CC = 3.3V
AC CHARACTERISTICS (V CC = 3.3V
MOTOROLA
Symbol
V CMR a
t JIT(PER)
t PLZ, HZ
t PZL, ZH
t JIT(CC)
Symbol
Z OUT
V CMR b
I CCQ
I CCA
t JIT( )
V OH
t LOCK
V PP
V OL
f refDC
V IH
t sk(o)
V IL
f VCO
f MAX
I IN
V PP
t ( )
tr, tf
t r , t f
BW
f ref
DC
V CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR range
and the input swing lies within the V PP (DC) specification.
The MPC9351 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V TT . Alternatively, the device drives up to two 50 series terminated transmission lines.
AC characteristics apply for parallel output termination of 50 to V TT
V CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V CMR range
and the input swing lies within the V PP (AC) specification. Violation of V CMR or V PP impacts static phase offset t ( ) .
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output Impedance
Input Leakage Current
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Input Frequency
VCO Frequency
Maximum Output Frequency
Reference Input Duty Cycle
Peak-to-Peak Input Voltage PCLK, PCLK
Common Mode Range
TCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-cycle jitter
Single Output Frequency Configuration
Period Jitter
Single Output Frequency Configuration
I/O Phase Jitter
Maximum PLL Lock Time
Characteristics
Characteristics
PCLK to EXT_FB
TCLK to EXT_FB
Freescale Semiconductor, Inc.
Static test mode
100 – 200 MHz
For More Information On This Product,
50 – 100 MHz
PCLK, PCLK
PCLK, PCLK
PCLK, PCLK
25 – 50 MHz
2 feedback
4 feedback
8 feedback
2 feedback
4 feedback
8 feedback
4 feedback
4 feedback
5%, T A = –40 to 85 C)
5%, T A = –40 to 85 C) a
2 output
4 output
8 output
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48.75
47.5
Min
250
Min
100
200
100
500
–50
+25
2.0
1.0
2.4
1.2
0.1
50
25
50
25
25
45
0
4
9.0 – 20.0
3.0 – 9.5
1.2 – 2.1
4.0 – 17
14 - 17
Typ
Typ
3.0
8.0
50
50
50
10
V CC + 0.3
V CC -0.6
V CC -0.9
51.75
1000
+150
+325
Max
0.55
0.30
Max
52.5
200
100
300
400
200
100
150
0.8
5.0
1.0
1.0
1.0
1.0
150
50
50
75
55
10
10
22
15
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
mV
mA
mA
mV
ms
ns
ps
ps
ps
ns
ns
ns
ps
ps
ps
W
%
%
%
%
V
V
V
V
V
V
V
A
TIMING SOLUTIONS
LVCMOS
LVCMOS
LVPECL
LVPECL
I OH =-24 mA b
I OL = 24 mA
I OL = 12 mA
V IN = V CC or GND
V CCA Pin
All V CC Pins
PLL_EN = 1
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
LVPECL
LVPECL
0.8 to 2.0V
0.55 to 2.4V
–3 db point of
PLL transfer
characteristic
RMS value
RMS value
RMS value
PLL locked
PLL locked
Condition
Condition