MC88LV915T_01 MOTOROLA [Motorola, Inc], MC88LV915T_01 Datasheet

MC88LV915T_01

Manufacturer Part Number

MC88LV915T_01

Description

Low Voltage Low Skew CMOS PLL Clock Driver, 3-State

Manufacturer

MOTOROLA [Motorola, Inc]

Datasheet

1.MC88LV915T_01.pdf (12 pages)

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SEMICONDUCTOR TECHNICAL DATA

lock its low skew outputs’ frequency and phase onto an input reference

clock. It is designed to provide clock distribution for high performance PC’s

and workstations.

clock input and distribute it with essentially zero delay to multiple

components on a board. The PLL also allows the MC88LV915T to multiply

a low frequency input clock and distribute it locally at a higher (2X) system

frequency. Multiple 88LV915’s can lock onto a single reference clock, which

is ideal for applications when a central system clock must be distributed

synchronously to multiple boards (see Figure 4 on Page 9).

phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”

frequency.

the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the

“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on

page 2). In most applications FREQ_SEL should be held high ( 1). If a low frequency reference clock input is used, holding

FREQ_SEL low ( 2) will allow the VCO to run in its optimal range (>20MHz).

88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low

frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing

(see detailed description on page 11).

OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC

input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.

low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees

a SYNC signal and full 5V V

Features

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

The MC88LV915T Clock Driver utilizes phase–locked loop technology to

The PLL allows the high current, low skew outputs to lock onto a single

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180

The VCO is designed to run optimally between 20 MHz and the 2X_Q F

The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the

A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go

Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t

specification, which defines the part–to–part skew)

Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

Input frequency range from 5MHz – 2X_Q FMAX spec.

Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180 phase shift) output available

All outputs have 36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are

TTL–level compatible. 88mA I

Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3–state) for board test purposes

Lock Indicator (LOCK) accuracy indicates a phase–locked state

Motorola, Inc. 2001

specifications guarantee 50

transmission line switching on the incident edge

max

specification. The wiring diagrams in Figure 2 detail

PLL CLOCK DRIVER

LOW SKEW CMOS

Order Number: MC88LV915T/D

Rev 3, 08/2001

Related parts for MC88LV915T_01

MC88LV915T_01 Summary of contents

Page 1

SEMICONDUCTOR TECHNICAL DATA The MC88LV915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock designed to provide clock distribution for high performance PC’s and workstations. The PLL ...

Page 2

PIN SUMMARY 2 Pinout: 28–Lead PLCC (Top View) FN SUFFIX PLASTIC PLCC CASE 776–02 MOTOROLA ...

Page 3

MOTOROLA MC88LV915T BLOCK DIAGRAM 3 ...

Page 4

MAXIMUM RATINGS* Symbol Supply Voltage Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) out I DC Input Current, Per Pin Output ...

Page 5

FREQUENCY SPECIFICATIONS ( Symbol Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output Fmax (‘Q’) Maximum Operating Frequency, Q0–Q3 Outputs NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition. AC ...

Page 6

Applications Information for All Versions Figure 1. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook–up configuration of Figure 2a on page 7) Timing Notes: The MC88LV915T aligns rising edges of the FEEDBACK input and SYNC input, therefore ...

Page 7

Figure 2a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back Figure 2b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back Figure 2c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back MOTOROLA 7 ...

Page 8

Figure 3. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV915T Notes Concerning Loop Filter and Board Layout Issues 1. Figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. The following ...

Page 9

Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T for Frequency Multiplication and Low Board–to–Board Skew MC88LV915T System Level Testing Functionality 3–state functionality has been added to the 100MHz version of the MC88LV915T to ease system board testing. ...

Page 10

OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776–02 ISSUE BRK –M– VIEW D– –T– VIEW S VIEW ...

Page 11

MOTOROLA NOTES 11 ...

Page 12

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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