PI90LV019L PERICOM [Pericom Semiconductor Corporation], PI90LV019L Datasheet

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PI90LV019L

Manufacturer Part Number
PI90LV019L
Description
Single Bus LVDS Transceiver
Manufacturer
PERICOM [Pericom Semiconductor Corporation]
Datasheet
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Features
• Balanced Output Impedance
• Light Bus Loading: 5pF typical
• Glitch-free power up/down (Driver Disabled)
• High Signaling Rate Capability: >500 Mbps
• Driver:
• Receiver:
• Bus terminal ESD exceeds 9kV
• Industrial Temperature Operation (–40°C to +85°C)
• Packaging: (Pb-free & Green available)
Block Diagram
– ±350mV Differential Swing into:
– 100-ohm load (PI90LV019)
– Accepts ±50mV (min.) Differential Swing with up to 2.0V
– Propagation Delay of 3.3ns typ.
– Low Voltage TTL (LVTTL) Outputs
– Open, Short, and Terminated Fail Safe
14-lead SOIC (W) and 14-lead TSSOP (L)
ground potential difference
06-0018
R OUT
D IN
DE
RE
D0+
D0–
RI+
RI–
1
Description
The PI90LV019, differential line driver and receiver (transceiver),
is compliant to IEEE1596.3 SCI and ANSI/TIA/
EIA-644LVDS standards. The logic interface provides maximum
flexibility resulting from four separate lines that are provided: D
DE, RE, and R
allows easy PCB routing for short stubs between the bus pins and
the connector.
The driver translates between TTL levels (single-ended) to Low
Voltage Differential Signaling levels. This allows for high-speed
operation, while consuming minimal power with reduced EMI. In
addition the differential signaling provides common mode noise
rejection of ±1V.
Pin Configuration
OUT
R
GND
OUT
DE
D
NC
NC
NC
. These devices also feature flow through which
IN
Single Bus LVDS Transceiver
1
2
3
4
5
6
7
14-Pin
L, W
14
13
12
11
10
9
8
NC
D
D
RI+
RI–
RE
V
PI90LV019
CC
O+
O–
PS8614C
03/06/06
IN
,

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