MC14070B_06 ONSEMI [ON Semiconductor], MC14070B_06 Datasheet

MC14070B_06

Manufacturer Part Number

MC14070B_06

Description

CMOS SSI Quad Exclusive OR and NOR Gates

Manufacturer

ONSEMI [ON Semiconductor]

Datasheet

1.MC14070B_06.pdf (7 pages)

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MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates

exclusive NOR gate are constructed with MOS P−channel and

N−channel enhancement mode devices in a single monolithic

structure. These complementary MOS logic gates find primary use

where low power dissipation and/or high noise immunity is desired.

Features

•

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V

to the range V

(e.g., either V

MAXIMUM RATINGS

October, 2006 − Rev. 7

Symbol

The MC14070B quad exclusive OR gate and the MC14077B quad

This device contains protection circuitry to guard against damage due to high

Unused inputs must always be tied to an appropriate logic voltage level

Schottky TTL Load Over the Rated Temperature Range

Supply Voltage Range = 3.0 Vdc to 18 Vdc

All Outputs Buffered

Capable of Driving Two Low−Power TTL Loads or One Low−Power

Double Diode Protection on All Inputs

MC14070B − Replacement for CD4030B and CD4070B Types

MC14077B − Replacement for CD4077B Type

Pb−Free Packages are Available

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

, V

, I

stg

out

DC Supply Voltage Range

Input or Output Voltage Range

Input or Output Current

Power Dissipation, per Package

Ambient Temperature Range

Storage Temperature Range

Lead Temperature

(DC or Transient)

(DC or Transient) per Pin

(Note 1)

(8−Second Soldering)

or V

v (V

). Unused outputs must be left open.

Parameter

or V

(Voltages Referenced to V

out

) v V

and V

−0.5 to V

−0.5 to +18.0

−55 to +125

−65 to +150

out

)

Value

± 10

500

260

should be constrained

+ 0.5

Unit

°C

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

WL, L

YY, Y

WW, W

ORDERING INFORMATION

http://onsemi.com

CASE 751A

SOEIAJ−14

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

CASE 646

CASE 965

P SUFFIX

D SUFFIX

F SUFFIX

PDIP−14

SOIC−14

Publication Order Number:

MC140xxBCP

DIAGRAMS

AWLYYWWG

MARKING

MC140xxB

AWLYWW

MC14070B/D

ALYWG

140xxBG

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MC14070B_06 Summary of contents

Page 1

MC14070B, MC14077B CMOS SSI Quad Exclusive “OR” and “NOR” Gates The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These complementary ...

Page 2

PIN ASSIGNMENT OUT 3 A OUT MC14070B QUAD Exclusive OR Gate ...

Page 3

ORDERING INFORMATION Device MC14070BCP MC14070BCPG MC14070BD MC14070BDG MC14070BDR2 MC14070BDR2G MC14070BFEL MC14070BFELG MC14077BCP MC14077BCPG MC14077BD MC14077BDG MC14077BDR2 MC14077BDR2G MC14077BFEL MC14077BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging ...

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MC14070B_06 datasheet download

MC14070B_06 ONSEMI [ON Semiconductor], MC14070B_06 Datasheet

MC14070B_06

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MC14070B_06 Summary of contents

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