MC14076B
4−Bit D−Type Register
with Three−State Outputs
operating synchronously from a common clock. OR gated
output−disable inputs force the outputs into a high−impedance state
for use in bus organized systems. OR gated data−disable inputs cause
the Q outputs to be fed back to the D inputs of the flip−flops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flip−flops simultaneously independent of the clock or disable inputs.
Features
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
MAXIMUM RATINGS
February, 2005 − Rev. 5
Symbol
V
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
I
The MC14076B 4−Bit Register consists of four D−type flip−flops
in
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Modes: Parallel Load and Do Nothing
Schottky TTL Load Over the Rated Temperature Range
Three−State Outputs with Gated Control Lines
Fully Independent Clock Allows Unrestricted Operation for the Two
Asynchronous Master Reset
Four Bus Buffer Registers
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Pb−Free Packages are Available*
Semiconductor Components Industries, LLC, 2005
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
http://onsemi.com
CASE 751B
CASE 648
D SUFFIX
P SUFFIX
SOIC−16
PDIP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
Publication Order Number:
16
1
16
1
DIAGRAMS
MARKING
MC14076BCP
AWLYYWW
AWLYWW
MC14076B/D
14076B