MC74HC32A_06 ONSEMI [ON Semiconductor], MC74HC32A_06 Datasheet

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MC74HC32A_06

Manufacturer Part Number
MC74HC32A_06
Description
Quad 2−Input OR Gate High−Performance Silicon−Gate CMOS
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet
MC74HC32A
Quad 2−Input OR Gate
High−Performance Silicon−Gate CMOS
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 9
The MC74HC32A is identical in pinout to the LS32. The device
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 48 FETs or 12 Equivalent Gates
Pb−Free Packages are Available
1
14
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
14
14
14
1
(Note: Microdot may be in either location)
1
1
ORDERING INFORMATION
1
A
L, WL
Y, YY
W, WW
G or G
http://onsemi.com
CASE 948G
CASE 751A
SOEIAJ−14
DT SUFFIX
TSSOP−14
CASE 646
CASE 965
N SUFFIX
D SUFFIX
F SUFFIX
SOIC−14
PDIP−14
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
14
1
14
1
14
1
14
DIAGRAMS
MC74HC32AN
AWLYYWWG
1
MARKING
MC74HC32A/D
74HC32A
AWLYWW
ALYWG
HC32AG
ALYWG
32A
HC
G

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MC74HC32A_06 Summary of contents

Page 1

MC74HC32A Quad 2−Input OR Gate High−Performance Silicon−Gate CMOS The MC74HC32A is identical in pinout to the LS32. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive Capability: ...

Page 2

Pinout: 14−Lead Packages (Top View FUNCTION TABLE Inputs ORDERING ...

Page 3

MAXIMUM RATINGS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter V Minimum High−Level Input Voltage IH V Maximum Low−Level Input Voltage IL V Minimum High−Level Output OH Voltage V Maximum Low−Level Output OL Voltage I Maximum Input Leakage Current in I Maximum ...

Page 5

INPUT 50 10% t PLH 90% OUTPUT Y 50% 10% t TLH Figure 1. Switching Waveforms OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 2. Test Circuit A B ...

Page 6

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 7

G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques ...

Page 8

K 14X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our ...

Page 9

0.13 (0.005) M 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products ...

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