M4T32-BR12SHX

Manufacturer Part NumberM4T32-BR12SHX
DescriptionSerial real-time clock with 44 bytes NVRAM and reset
ManufacturerSTMICROELECTRONICS [STMicroelectronics]
M4T32-BR12SHX datasheet
 
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Serial real-time clock with 44 bytes NVRAM and reset
Features
Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
32KHz crystal oscillator integrating load
capacitance (12.5pF) providing exceptional
oscillator stability and high crystal series
resistance operation
Serial peripheral interface (2MHz SPI)
Ultra-low battery supply current of 500nA (max)
2.7 to 5.5V operating voltage
2.5 to 5.5V oscillator operating voltage
Battery low flag
Automatic switchover and deselect circuitry
44 bytes of general purpose RAM
Programmable alarm and interrupt function
(valid even during battery back-up mode)
Accurate programmable watchdog timer (from
62.5ms to 128s)
Microprocessor power-on reset
Choice of power-fail deselect voltages
(V
= 2.7 to 5.5V):
CC
– THS = V
; 2.55V
V
SS
PFD
– THS = V
; 4.20V
V
CC
PFD
Packaging includes a 28-lead SOIC and
®
SNAPHAT
top (to be ordered separately) or
16-lead SOIC
28-lead SOIC package provides direct
connection for a SNAPHAT top which contains
the battery and crystal
RoHS compliant
– Lead-free second level interconnect
November 2007
2.70V
4.50V
Rev 5
M41T94
16
1
SO16 (MQ)
SNAPHAT (SH)
battery & crystal
28
1
SOH28 (MH)
1/41
www.st.com
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M4T32-BR12SHX Summary of contents

  • Page 1

    Serial real-time clock with 44 bytes NVRAM and reset Features ■ Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century ■ 32KHz crystal oscillator integrating load capacitance (12.5pF) providing exceptional oscillator stability and high crystal ...

  • Page 2

    Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    Description The M41T94 is a serial real-time clock with 44 bytes of NVRAM and a RESET output. A built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 4 on page 19) are used for ...

  • Page 7

    Figure 1. Logic diagram (1) XI (1) XO SCL SDI E RSTIN1 RSTIN2 WDI THS 1. For SO16 package only. Figure 2. 16-pin SOIC connections XO RST WDI RSTIN1 RSTIN2 V BAT BAT RST ...

  • Page 8

    Table 1. Signal names E IRQ/FT/OUT RST RSTIN1 RSTIN2 SCL SDI SDO SQW THS WDI (1) XI (1) XO (1) V BAT For SO16 package only. Figure 3. 28-pin SOIC connections 8/41 Chip enable Interrupt/frequency ...

  • Page 9

    Figure 4. Block diagram E SDO SPI SDI INTERFACE SCL 32KHz Crystal OSCILLATOR WDI BAT RSTIN1 RSTIN2 1. Open drain output Figure 5. Hardware hookup D SPI Interface with (CPOL, CPHA) ( ('0','0') or ('1','1') ...

  • Page 10

    Table 2. Function table Mode E Disable reset H WRITE L READ L 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ. Figure 6. Data and clock timing CPOL ...

  • Page 11

    Signal description 2.1 Serial data output (SDO) The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. 2.2 Serial data input (SDI) The input ...

  • Page 12

    Operation The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL, SDI and SDO (see the ...

  • Page 13

    SPI bus characteristics The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: Serial data input (SDI), Serial data output (SDO), Serial clock (SCL) and a Chip Enable (E). ...

  • Page 14

    Figure 8. Output timing requirements E SCL tCLQV tCLQX MSB OUT SDO ADDR. LSB IN SDI 14/41 tCH tCL LSB OUT tQLQH tQHQL tEHQZ AI04634 ...

  • Page 15

    Table 3. AC characteristics Symbol f Serial clock input frequency SCL (2) t Clock high CH (3) t Clock transition (fall time) CHCL t Serial clock input high to input data transition CHDX t Serial clock input high to chip ...

  • Page 16

    Read and write cycles Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial Data Output (SDO). Any data transfer considers the first bit to define whether a READ or WRITE ...

  • Page 17

    Figure 9. Read mode sequence SCL W/R BIT 7 BIT ADDRESS SDI MSB SDO HIGH IMPEDANCE Figure 10. Write mode sequence SCL 7 BIT ADDR W/R ...

  • Page 18

    Clock operations The eight byte clock register (see read the date and time from the clock binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Bits D6 and ...

  • Page 19

    Table 4. Clock register map Addr 00h 0.1 seconds 01h ST 10 seconds 02h 0 10 minutes 03h CEB CB 10 Hours 04h 05h date 06h 07h 10 ...

  • Page 20

    Setting alarm clock registers Address locations 0Ah-0Eh contain the Alarm settings. The Alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, ...

  • Page 21

    Figure 11. Alarm interrupt reset waveforms 0Eh ACTIVE FLAG IRQ/FT/OUT Figure 12. Back-up mode alarm waveforms PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT 0Fh HIGH-Z 10h HIGH-Z AI03664 tREC ...

  • Page 22

    Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog register, address 09h. bits BMB4-BMB0 store a binary multiplier and ...

  • Page 23

    Table 6. Square wave output frequency RS3 4.6 Power-on reset The M41T94 continuously monitors V the RST pulls low (open drain) and remains low ...

  • Page 24

    Figure 13. RSTIN1 and RSTIN2 timing waveforms RSTIN1 RSTIN2 (1) RST Table 7. Reset AC characteristics Symbol (2) t RSTIN1 low to RSTIN1 high RLRH1 (3) t RSTIN2 low to RSTIN2 high RLRH2 (4) t RSTIN1 high to RST high ...

  • Page 25

    Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range ...

  • Page 26

    Figure 14. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 Figure 15. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 4.9 Century bit Bits D7 and D6 of clock register 03h ...

  • Page 27

    Output driver pin When the FT bit, AFE bit and Watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents the Control register. In other words, when D7 (OUT bit) ...

  • Page 28

    Initial power-on defaults Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state: ST, ...

  • Page 29

    Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...

  • Page 30

    DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under ...

  • Page 31

    Table 13. DC characteristics Symb. Parameter Battery current OSC on I BAT Battery current OSC off I Supply current CC1 I Supply current (standby) CC2 (2) I Input leakage current LI (3) I Output leakage current LO V Input high ...

  • Page 32

    Figure 17. Power down/up mode AC waveforms PFD (max) V PFD (min INPUTS RST OUTPUTS (PER CONTROL INPUT) Table 15. Power down/up AC characteristics Symbol ( (max PFD (3) t ...

  • Page 33

    Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...

  • Page 34

    Figure 18. SO16 – 16-lead plastic small outline package outline 1. Drawing is not to scale. Table 16. SO16 – 16-lead Plastic small outline package mechanical data Symbol 34/41 ...

  • Page 35

    Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline SOH-A 1. Drawing is not to scale. Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package mechanical data millimeters Symbol Typ ...

  • Page 36

    Figure 20. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline 1. Drawing is not to scale. Table 18. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data Symbol Typ ...

  • Page 37

    Figure 21. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline 1. Drawing is not to scale. Table 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data millimeters Symbol Typ Min A ...

  • Page 38

    ... Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 21. SNAPHAT battery table Part number M4T28-BR12SH1 M4T32-BR12SHx 38/41 M41T V 4.50V PFD V 2.70V PFD ® ...

  • Page 39

    References The crystal supplier KDS as cited in supplied) on page 31 Table 14: Crystal electrical characteristics (externally can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. 39/41 ...

  • Page 40

    Revision history Table 22. Document revision history Date Revision April 2002 25-Apr-02 03-Jul-02 06-Nov-02 26-Mar-03 28-Apr-03 15-Jun-04 29-Aug-2006 09-Nov-2007 40/41 1.0 First edition Adjust graphic (Figure 4 on page 1.1 Table 20 on page 38); adjust characteristics Table 14 ...

  • Page 41

    Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...