M4T32-BR12SHX STMICROELECTRONICS [STMicroelectronics], M4T32-BR12SHX Datasheet - Page 18

• Manufacturer Part Number: M4T32-BR12SHX
• Description: Serial real-time clock with 44 bytes NVRAM and reset
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

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4.1
4.2
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Clock operations
The eight byte clock register (see
read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths
of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Bits
D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit
(CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from
'0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is
set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the Day (day of
week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The
ninth clock register is the Control register (this is described in the clock calibration section).
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. If the device is expected to spend a significant amount of time on the shelf,
the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator
restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. The
Control register (Address location 08h) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the eight clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. This will prevent a transition of data during the READ.
Power-down time-stamp
When a power failure occurs, the Halt Update bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the clock registers, and will allow the user to read the
exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to
update the clock registers with the current time. For more information, see Application Note
AN1572.
Clock registers
The M41T94 offers 20 internal registers which contain clock, Alarm, Watchdog, Flag,
Square Wave and Control data (see
locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT
except that they are updated periodically by the simultaneous transfer of the incremented
internal copy. The internal divider (or clock) chain will be reset upon the completion of a
WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the clock addresses (00h
to 07h) are being written. The update will resume either due to a deselect condition or when
the pointer increments to a non-clock or RAM address.
Clock and Alarm registers store data in BCD. Control, Watchdog and Square Wave registers
store data in Binary format.
™
cells). The external copies are independent of internal functions
Table 4 on page
Table 4 on page
19) is used to both set the clock and to
19). These registers are memory