M4T32-BR12SHX STMICROELECTRONICS [STMicroelectronics], M4T32-BR12SHX Datasheet - Page 27

• Manufacturer Part Number: M4T32-BR12SHX
• Description: Serial real-time clock with 44 bytes NVRAM and reset
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

4.10
Note:
4.11
Note:
4.12
Output driver pin
When the FT bit, AFE bit and Watchdog register are not set, the IRQ/FT/OUT pin becomes
an output driver that reflects the contents of D7 of the Control register. In other words, when
D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will
be driven low.
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
Battery low warning
The M41T94 automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of Flags register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery Back-up mode, the battery should be replaced. The SNAPHAT top may be replaced
while V
This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is
disconnected.
The M41T94 only monitors the battery when a nominal V
applications which require extensive durations in the battery Back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
t
Bit D7 of clock register 04h contains the t
continuation of the deselect time after V
time before WRITEs may again be performed to the device after a power-down condition.
The t
Table on page
REC
REC
CC
bit
bit will allow the user to set the length of this deselect time as defined by Table
CC
is applied to the device.
is supplied. In order to insure data integrity during subsequent periods of
28.
CC
REC
reaches V
bit (TR). t
PFD
REC
. This allows for a voltage setting
CC
refers to the automatic
is applied to the device. Thus
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