74LVC2G32DC NXP [NXP Semiconductors], 74LVC2G32DC Datasheet

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74LVC2G32DC

Manufacturer Part Number
74LVC2G32DC
Description
Dual 2-input OR gate
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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1. General description
2. Features
The 74LVC2G32 provides a 2-input OR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
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74LVC2G32
Dual 2-input OR gate
Rev. 05 — 4 September 2007
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs in the Power-down mode
High noise immunity
CMOS low power consumption
Complies with JEDEC standard:
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
N
N
N
N
N
24 mA output drive (V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74LVC2G32DC Summary of contents

Page 1

Dual 2-input OR gate Rev. 05 — 4 September 2007 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3 devices. This feature allows the use of ...

Page 2

... Package Temperature range Name 74LVC2G32DP +125 C 74LVC2G32DC +125 C 74LVC2G32GT +125 C 74LVC2G32GM +125 C 4. Marking Table 2. Marking Type number 74LVC2G32DP 74LVC2G32DC 74LVC2G32GT 74LVC2G32GM 5. Functional diagram mna733 Fig 1. Logic symbol Fig 3. Logic diagram (one gate) ...

Page 3

NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration TSSOP8 and VSSOP8 74LVC2G32 GND 4 Transparent top view Fig 5. Pin configuration XSON8 6.2 Pin description Table 3. Pin description Symbol Pin ...

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NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum ...

Page 5

NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics ...

Page 6

NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC I additional supply current CC C input capacitance +125 ...

Page 7

NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nA nY; see power ...

Page 8

NXP Semiconductors Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V Test data is given in Table 10. Definitions ...

Page 9

NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions ...

Page 10

NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 ...

Page 11

NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A ...

Page 12

NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area ...

Page 13

NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID ...

Page 14

NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 15

NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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