74LVC2G66DCV66 NXP [NXP Semiconductors], 74LVC2G66DCV66 Datasheet

no-image

74LVC2G66DCV66

Manufacturer Part Number
74LVC2G66DCV66
Description
Bilateral switch
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1. General description
2. Features and benefits
The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device.
The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire V
74LVC2G66
Bilateral switch
Rev. 5 — 16 June 2010
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
ESD protection:
Enable input accepts voltages up to 5.5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
7.5 Ω (typical) at V
6.5 Ω (typical) at V
6 Ω (typical) at V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
CC
CC
= 5 V
= 2.7 V
= 3.3 V
CC
range from 1.65 V to 5.5 V.
Product data sheet

Related parts for 74LVC2G66DCV66

74LVC2G66DCV66 Summary of contents

Page 1

Bilateral switch Rev. 5 — 16 June 2010 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and ...

Page 2

NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC2G66DP −40 °C to +125 °C 74LVC2G66DC −40 °C to +125 °C 74LVC2G66GT −40 °C to +125 °C 74LVC2G66GD −40 ...

Page 3

NXP Semiconductors Fig 3. Logic diagram (one switch) 6. Pinning information 6.1 Pinning 74LVC2G66 GND 4 001aaa529 Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC2G66 GND 4 Transparent ...

Page 4

NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT996-2 and SOT833 GND Functional description [1] Table 4. Function ...

Page 5

NXP Semiconductors 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb Δt/ΔV input transition rise and fall rate [1] To avoid sinking GND ...

Page 6

NXP Semiconductors Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance C OFF-state S(OFF) capacitance C ON-state S(ON) capacitance [1] All typical values are ...

Page 7

NXP Semiconductors 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Symbol Parameter Conditions R ON resistance V = GND to V ON(peak) I (peak ...

Page 8

NXP Semiconductors 10.3 ON resistance test circuit and graphs GND Fig 10. Test circuit for measuring ON resistance ...

Page 9

NXP Semiconductors (Ω) 11 (1) 9 (2) ( 0.5 1.0 1.5 2.0 = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. ...

Page 10

NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nY; pd ...

Page 11

NXP Semiconductors Σ{(C ) × V × sum of the outputs. L S(ON 11.1 Waveforms and test circuit Measurement points are given in Logic levels: V ...

Page 12

NXP Semiconductors negative positive Test data is given in Table 11. Definitions for test circuit Load resistor Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance ...

Page 13

NXP Semiconductors 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T Symbol Parameter THD total harmonic distortion −3 dB frequency response f (−3dB) α isolation (OFF-state) ...

Page 14

NXP Semiconductors Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T Symbol Parameter V crosstalk voltage ct Xtalk crosstalk Q charge injection inj 74LVC2G66 Product data sheet …continued Conditions between ...

Page 15

NXP Semiconductors 11.3 Test circuits Test conditions 1. 1.4 V (p-p 2 (p-p 2.5 V (p-p ...

Page 16

NXP Semiconductors G Fig 23. Test circuit for measuring crosstalk voltage (between digital inputs and switch 600 Ω 20 log ( log Fig 24. Test ...

Page 17

NXP Semiconductors G a. Test circuit logic input (nE) b. Input and output pulse definitions = ΔV × inj O L ΔV = output voltage variation generator resistance. gen V = generator voltage. gen ...

Page 18

NXP Semiconductors 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions ...

Page 19

NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT ...

Page 20

NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) ...

Page 21

NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT A ...

Page 22

NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal ...

Page 23

NXP Semiconductors 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release ...

Page 24

NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 25

NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales ...

Page 26

NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...

Related keywords