74LVC2T45DC

Manufacturer Part Number74LVC2T45DC
DescriptionDual supply translating transceiver; 3-state
ManufacturerNXP [NXP Semiconductors]
74LVC2T45DC datasheet
 


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74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 03 — 19 January 2010
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V
and V
CC(B)
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to V
pins nB are referenced to V
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using I
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features
Wide supply voltage range:
V
CC(A)
V
CC(B)
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114E Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
). Both V
and V
can be supplied at any voltage between 1.2 V and
CC(A)
CC(B)
. A HIGH on DIR allows transmission from nA to nB and a
CC(B)
: 1.2 V to 5.5 V
: 1.2 V to 5.5 V
Product data sheet
CC(A)
and
CC(A)
. The I
OFF
OFF
or V
are at
CC(A)
CC(B)

74LVC2T45DC Summary of contents

  • Page 1

    Dual supply translating transceiver; 3-state Rev. 03 — 19 January 2010 1. General description The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports ...

  • Page 2

    ... Marking Table 2. Marking Type number 74LVC2T45DC 74LVCH2T45DC 74LVC2T45GT 74LVCH2T45GT 74LVC2T45GD 74LVCH2T45GD 74LVC2T45GM 74LVCH2T45GM 74LVC_LVCH2T45_3 Product data sheet 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state = 3.0 V) ...

  • Page 3

    NXP Semiconductors 5. Functional diagram 5 DIR CC(A) Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC2T45 74LVCH2T45 V 1 CC( GND 4 001aai904 Fig 3. Pin configuration SOT765-1 ...

  • Page 4

    NXP Semiconductors 74LVC2T45 74LVCH2T45 V 1 CC( GND 4 Transparent top view Fig 5. Pin configuration SOT996-2 (XSON8U) 6.2 Pin description Table 3. Pin description Symbol Pin SOT765-1, SOT833-1 and SOT996 CC( ...

  • Page 5

    NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage A CC(A) V supply voltage B CC(B) ...

  • Page 6

    NXP Semiconductors 10. Static characteristics Table 7. Typical static characteristics recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage ...

  • Page 7

    NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level data input IH input voltage V = 1.2 V CCI 1.95 ...

  • Page 8

    NXP Semiconductors Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 100 μ ...

  • Page 9

    NXP Semiconductors Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I power-off A port; V OFF I leakage CC(A) current V = 1.2 ...

  • Page 10

    NXP Semiconductors 11. Dynamic characteristics Table 9. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t LOW to HIGH PLH propagation delay B to ...

  • Page 11

    NXP Semiconductors Table 11. Typical power dissipation capacitance at V Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C power dissipation A port: (direction A to B); PD capacitance B port: (direction ...

  • Page 12

    NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +85 °C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to HIGH DIR to A PZH propagation delay ...

  • Page 13

    NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +85 °C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t LOW to OFF-state DIR to A PLZ propagation delay ...

  • Page 14

    NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +125 °C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to LOW DIR to A PZL propagation delay ...

  • Page 15

    NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +125 °C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to HIGH DIR to A PZH propagation delay ...

  • Page 16

    NXP Semiconductors Table 14. Measurement points [1] Supply voltage Input CC(A) CC( 1.6 V 0.5V CCI 1. 2.7 V 0.5V CCI 3 5.5 V 0.5V CCI [1] V ...

  • Page 17

    NXP Semiconductors 13. Typical propagation delay characteristics 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns ...

  • Page 18

    NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns ...

  • Page 19

    NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns ...

  • Page 20

    NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns ...

  • Page 21

    NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns ...

  • Page 22

    NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns ...

  • Page 23

    NXP Semiconductors 14. Application information 14.1 Unidirectional logic level-shifting application The circuit given unidirectional logic level-shifting application. V CC1 V CC1 system-1 Fig 16. Unidirectional logic level-shifting application Table 16. Description of unidirectional logic level-shifting application Pin ...

  • Page 24

    NXP Semiconductors V CC1 I/O-1 PULL-UP/DOWN DIR CTRL system-1 Pull-up or pull-down only needed for 74LVC2T45. Fig 17. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 ...

  • Page 25

    NXP Semiconductors 14.4 Enable times Calculate the enable times for the 74LVC2T45; 74LVCH2T45 using the following formulas: • t (DIR PZH • t (DIR PZL • t (DIR ...

  • Page 26

    NXP Semiconductors 15. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index DIMENSIONS (mm are the original dimensions ...

  • Page 27

    NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) ...

  • Page 28

    NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT A ...

  • Page 29

    NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 ...

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    NXP Semiconductors 16. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 20. Revision history Document ...

  • Page 31

    NXP Semiconductors 18. Legal information 18.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

  • Page 32

    NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...