AD7346B AD [Analog Devices], AD7346B Datasheet

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AD7346B

Manufacturer Part Number
AD7346B
Description
2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
Manufacturer
AD [Analog Devices]
Datasheet
REV PrA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Preliminary Technical Data
FEATURES
Integrated front End for Single Pair or Two Pair HDSL
Systems
Meets ETSI Specifications
Supports 1168 kbps and 2.32 Mbps
Programmable Filtering Supports Adaptive HDSL
Transmit and Receive Signal Path Functions
Normal Loopback
Serial Interface to Digital Transceivers
Single 3 V Power Supply
Receive Hybrid Amplifier, PGA, ADC and Adaptable
Transmit DAC, Adaptable Filter and Differential
P W RD O W N B
R EF -CO M
Outputs
A DC C LK
R ES E T B
Filter
T xS YN C
T xD A T A
C M -L V L
S P IC LK
T xC LK
C AP -T
C AP -B
V RE F
S CL K
S DO
T FS
D R
D R
D T
V DR IV E
1 2-B it A D C
S P I
PRELIMINARY TECHNICAL DATA
T x-D E CO U P
C on trol/
C on figu ratio n
1 4-B it D A C
B uffer
A DC
FUNCTIONAL BLOCK DIAGRAM
4 P ole A da ptive
B utterw orth Filter
6 P ole A da ptive
B esse l Filte r
GENERAL DESCRIPTION
The AD5011 is an analog front end for two pair or single
pair HDSL applications that use 1168 kbps or 2.32 Mbps
data rates. The device integrates all the transmit and receive
functional blocks. A standard serial interface is used to
communicate with the DAC and ADC. The filters in both
the transmit and receive paths are programmable which
allows adaptive HDSL to be performed also. The part is
available in a 48-pin LQFP package and is specified for a
temperature range of -40
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: hppt://www.analog.com
2 Pair/1 Pair ETSI Compatible
HDSL Analog Front End
P G A
0 dB
-6 dB
P G A
-6 dB
-3 dB
0 dB
+3 d B
+6 d B
o
C to +85
L in e
D rive r
H ybrid
o
C.
AD5011
Fax: 781/326-8703
D RV -O U T P
D RV -O U T N
H YBIN-2 B
H YBIN-2 A
H YBIN-1 A
H YBIN-1 B

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AD7346B Summary of contents

Page 1

PRELIMINARY TECHNICAL DATA Preliminary Technical Data FEATURES Integrated front End for Single Pair or Two Pair HDSL Systems Meets ETSI Specifications Supports 1168 kbps and 2.32 Mbps Programmable Filtering Supports Adaptive HDSL Transmit and Receive Signal Path Functions Receive Hybrid ...

Page 2

PRELIMINARY TECHNICAL DATA AD5011–SPECIFICATIONS Parameter TRANSMIT CHANNEL 2 Signal to Noise 2 Total Harmonic Distortion TRANSMIT DAC Resolution Clock Frequency Coding 3 Output Update Rate Output Voltage TRANSMIT FILTER 4 Cutoff Frequency Corner Frequency Accuracy Adjacent Corner Step 5 LINE ...

Page 3

... The PGA gain is set by setting the PGA-GC bits in the control register. 8 The input switching threshold voltage is approximately 1 allow interfacing to 2.5 V and 3.3 V logic. 9 The output level is determined by the voltage on the logic supply pin V Specifications subject to change without notice. REV PrA AD7346B Units Test Conditions/Comments Min Typ Max VDD - 0.3 ...

Page 4

AD5011 TIMING CHARACTERISTICS Limit MIN MAX Parameter (B Version) ADCCLK <= 1160kHz t 1.5 2 2.5 3 26.939 1160 kHz < ...

Page 5

PRELIMINARY TECHNICAL DATA SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges Figure 2. ...

Page 6

AD5011 Mnemonic Function POWER SUPPLY VDRIVE Digital output drive level. AGND Analog power supply. AGND Analog Ground. DVDD Positive power supply for the digital section Digital Ground. TRANSMIT CHANNEL TxDATA Transmit data input ...

Page 7

PRELIMINARY TECHNICAL DATA Serial Register SEL[2:0]=000 SEL[2:0]=001 Control Reg Tx Prog Filt Reg D[15 D[14] SEL[ SEL[ D[13] SEL[ SEL[ D[12] SEL[ SEL[ D[11] ...

Page 8

AD5011 GGA-GC2 TPFD [7:0] RPFD[0: ...

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