ADCS9888CVH-140 NSC [National Semiconductor], ADCS9888CVH-140 Datasheet
ADCS9888CVH-140
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ADCS9888CVH-140 Summary of contents
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... Applications n LCD flat panel monitors n Video projectors n Plasma display panels n Video capture hardware n RGB and YUV video processing ≤ +70˚C A Device Marking ADCS9888CVH-205 ADCS9888CVH-170 ADCS9888CVH-140 DS200628 March 2005 8 bits x 3 channels 205 MHz 500 MHz 570 ps p-p 3 3 3.6 V 1.3W 20062801 NSC Drawing VLA128A www ...
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Simplified Block Diagram www.national.com 2 20062802 ...
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Connection Diagram 3 20062803 www.national.com ...
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Pin Descriptions Pin Label Analog Video Inputs 5 R AIN0 13 G AIN0 20 B AIN0 8 R AIN1 17 G AIN1 23 B AIN1 Analog Video Sync 12 SOGIN0 16 SOGIN1 Sync/Clock Inputs 45 HSYNC0 44 VSYNC0 43 HSYNC1 ...
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Pin Descriptions (Continued) Pin Label 53 COAST Digital Input PLL Clock Generator Coast Input. When enabled via Register 0Fh, Bit 5, 54 CKEXT Digital Input External Clock Input (Optional). This input can be used to provide an 29 CKINV Digital ...
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Pin Descriptions (Continued) Pin Label Data Clock Output 123 DATACK 124 DATACK_B Digital Data Outputs 113-120 D _A(7:0) R 103-110 D _B(7:0) R 90-97 D _A(7:0) G 80-87 D _B(7:0) G 70-77 D _A(7:0) B 57-64 D _B(7:0) B Voltage ...
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Pin Descriptions (Continued) Pin Label Power Supply 10, 14, 18, V Power D 21, 25, 26, 34, 37 Supply 56, 69, 79, 89, 98, V Power DD 102, 112, 122 Supply 47, 48 Power D ...
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... Input Full-Scale Matching Offset Adjustment Range INTERNAL VOLTAGE REFERENCE CHARACTERISTICS V Output Voltage REF Temperature Coefficient www.national.com (Notes 2, Machine Model Soldering Information Storage Temperature Operating Ratings Operating Temperature Range 3.6V ADCS9888CVH + −0. +0.3V V Supply Voltage D PV Supply Voltage −0. Supply Voltage ± ...
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AC Electrical Characteristics The following specifications apply for GND = fied. Boldface limits apply for Symbol Parameter Maximum Conversion Rate Minimum Conversion Rate Data to Clock Skew t BUFF t STAH t DHO ...
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DC and Logic Electrical Characteristics The following specifications apply for GND = fied. Boldface limits apply for Symbol Parameter I I/O Supply Current DD IP PLL Supply Current VD Total Power Dissipation Power ...
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Analog Channel Characteristics Note 8: Typical figures are 25˚C, with the ADC Clock at the stated speed, and represent most likely parametric norm Note 9: Test limits are guaranteed to National’s AOQL (Average ...
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Timing Diagrams Single Channel Mode - 2 Pixels per Clock (Even Pixels) www.national.com Single Channel Mode 12 20062805 20062806 ...
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Timing Diagrams (Continued) Single Channel Mode - 2 Pixels per Clock (Odd Pixels) Dual Channel Mode - Interleaved Outputs 13 20062807 20062808 www.national.com ...
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Timing Diagrams (Continued) Dual Channel Mode - Interleaved Outputs - 2 Pixels/Clock - Even Pixels www.national.com Dual Channel Mode - Parallel Outputs 14 20062809 20062810 ...
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Timing Diagrams (Continued) Dual Channel Mode - Interleaved Outputs - 2 Pixels/Clock - Odd Pixels Dual Channel Mode - Parallel Outputs - 2 Pixels/Clock - Even Pixels 15 20062811 20062812 www.national.com ...
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Timing Diagrams (Continued) Dual Channel Mode - Parallel Outputs - 2 Pixels/Clock - Odd Pixels www.national.com 4:2:2 Output Mode 16 20062813 20062814 ...
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Timing Diagrams (Continued) Data Output Timing Configuration Register Serial Timing Serial Interface Protocol 17 20062815 20062816 20062817 www.national.com ...
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Configuration Register Descriptions Address Write/Read Bits (Hex) or Read Only 00H RO 7:0 01H W/R 7:0 02H W/R 7:4 03H W/R 7:6 5:3 04H W/R 7:3 05H W/R 7:0 06H W/R 7:0 07H W/R 7:0 08H W/R 7:0 09H W/R ...
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Configuration Register Descriptions Address Write/Read Bits (Hex) or Read Only 0BH W/R 7:1 OCH W/R 7:1 ODH W/R 7:1 OEH W (Continued) POR Value Name 1000000* Red Offset Controls the DC offset ...
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Configuration Register Descriptions Address Write/Read Bits (Hex) or Read Only 0FH W 10H W/R 7 11H W/R 7:0 12H W/R 7:0 13H W/R 7:0 www.national.com (Continued) POR Value Name 0******* Clamp ...
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Configuration Register Descriptions Address Write/Read Bits (Hex) or Read Only 14H (Continued) POR Value Name Sync Detect Hsync Detect activity is detected on the HSYNC Status input pin. 0 ...
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Configuration Register Descriptions Address Write/Read Bits (Hex) or Read Only 15H W 2:1 0 16H W/R 7:0 17H W/R 7:0 18H RO 7:0 19H RO 7:0 www.national.com (Continued) POR Value Name 1******* Channel Mode Sets ...
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Application Information 1.0 INTRODUCTION The ADCS9888 is a complete 8 bit, 205 MSPS monolithic analog front end for capturing analog component video in digital video applications. The high sampling rate allows it to support video capture at full frame rate ...
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Application Information In dual channel output modes, if Register 15H, Bit 5 is set to one, then HSOUT will transition on the rising edge of DATACK instead of the falling edge as shown in the timing diagrams. All DATA and ...
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Application Information The Sync Slicer output has the same polarity as the input signal. “Normal” video with white positive and black negative will produce sync pulses that are active low. Normal synchro- nization signals will be mainly high with pulses ...
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Application Information 4.1 PLL The PLL generates a high frequency pixel clock that is frequency locked and phase aligned to the horizontal sync signal. The main controls for the PLL are as described in the follow- ing subsections. 4.1.1 PLL ...
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Application Information 4.1.6 Pre-Coast and Post-Coast When Vsync is used as the coast source, the coast signal can be extended earlier and later by setting the Pre-Coast and Post-Coast settings in Registers 12h and 13h. This feature requires the chip ...
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Application Information 4.2 Pixel Clock Generation And Timing AdjustmenT Several features are provided that are related to the pixel clock timing. These include: • Clock Phase Adjust • CKINV - This is discussed in more detail in the next section, ...
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Application Information Bit 7 Bit 6 Bit 5 Bit 4 Bit 6.2.5 Register Address BYTE ADCS9888 register addresses are an 8 bit value. Please refer to the Register Address ...
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Application Information www.national.com (Continued) Write to Single Register 30 20062824 ...
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Application Information (Continued) Write to Multiple (3) Registers 31 20062825 www.national.com ...
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Application Information www.national.com (Continued) Read from Single Register 32 20062822 ...
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Application Information 6.3.5 Serial Clock Input Noise Filter Because the serial clock and data lines are resistively pulled power bus, there is a possibility that noise will be coupled into the clock or data lines when all ...
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Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and ...